AD6676EBZ datasheet(40/90 Pages) AD

40 / 90 page

AD6676

Data Sheet

Rev. A | Page 40 of 90

Example

Calculate the NCO MIX1 and MIX2 values along with FIF_NCO

and fOFFSET with the following AD6676 configuration: FIF =

140 MHz, FADC = 3200 MHz, and decimation factor of 16 (that

is, fDATA_IQ = 200 MSPS).

•

Substituting FIF and FADC values in Equation 8 results in

MIX1 = 3.

•

Substituting these values in Equation 9 (noting that M =

4096 for DEC_MODE = 3 results in MIX2 = −13).

•

Substituting MIX1 and MIX2 values into Equation 10

results in FIF_NCO = 139.84375 MHz.

•

Substituting FIF and FIF_NCO values in Equation 11 results in

fOFFSET = 156.25 kHz.

NCO Phase Synchronization

The AD6676 coarse and fine tuning NCOs can be set to an

initial phase after synchronization with an external SYSREF

signal. The initial phase of the coarse tuning NCO is set via

MIX1_INIT, with an LSB corresponding to 1/64th of a cycle. The

initial phase of the fine tuning NCO is set via MIX2_INIT_x,

with an LSB corresponding to 1/1024th of a cycle.

Digital Filter Modes

The AD6676 digital filter path is designed to provide sufficient

stop band rejection of the Σ-Δ ADC shaped out-of-band noise

as well as any spurious noise that otherwise might alias back

into the desired pass band region after decimation and limit the

actual NSD performance. The filter path supports decimation

factors of 12, 16, 24, and 32 depending on the DEC_MODE

setting. The complex output of the coarse QDDC feeds a pair of

symmetrical FIR decimation filters divided into three stages, as

shown in Figure 103. The first stage is a decimate by 3 or by 4

filter, depending on whether the desired decimation factor is

divisible by three. The second and third stages consists of two

cascaded decimate by 2 filters with the third stage outputs

supporting the decimate by 12 and by 16 options. A bypassable

fourth stage provides the decimate by 24 and by 32 options.

The normalized pass band and wideband folded frequency

response for each filter mode are shown in Figure 105 through

Figure 113. Note the following observations:

•

All filter responses provide a linear phase response over its

pass band.

•

The usable IF bandwidth depends on the DEC_MODE as

well as the minimum acceptable pass band ripple and stop

band rejection requirements. Table 14 provides the

normalized usable complex bandwidth vs. DEC_MODE for

stop band rejections of greater than 85 dB and 60 dB.

•

The last filter stage sets the usable bandwidth and stop

band rejection because it has the most aggressive transition

band specifications. For this reason, the decimation factors

of 12 and 16 have the same normalized usable bandwidths

as does decimation factors of 24 and 32.

•

Wide IF bandwidths (MHz) are supported when operating

at lower decimation factors along with a high FADC.

•

It is worth noting that many applications requiring wider

IF bandwidth may tolerate reduced ripple and rejection as

the digital filter response enters its transition region. The

reason is that the Σ-Δ ADC achievable NSD performance

at the IF pass band edges also degrades as its oversampling

ratio is reduced, thus still dominating relative to any

aliased noise due to reduced filter stop band rejection.

Table 14. Usable Normalized Complex Bandwidth vs.

Decimation Factor

DEC_MODE

Decimation

Factor

DATA_IQ

BW (>85 dB

Rejection)

BW (>60 dB

Rejection)

0.814

0.834

0.814

0.834

0.571

0.617

0.571

0.617

Total Pipeline Latency

The digital filter path dominates the latency of the AD6676

whereas the JESD204B PHY adds a few samples of delay and

the ADC delay is a fraction of an output sample. The latency

between the ADC and digital filter output is fixed with the only

nondeterministic delay being associated with the JESD204B

PHY clock and lane FIFOs before synchronization. See the

Synchronization Using SYSREF section for additional

information. Table 15 provides the nominal pipeline delay

associated with each DEC_MODE. Note that although all

DEC_MODE settings provide similar delays relative to the

output data rate, fDATA_IQ, applications that require shorter

absolute time delays may consider using a lower decimation

factor to reduce the absolute delay by 2×.

Table 15. Nominal Pipeline Latency vs. DEC_MODE

(Sample Delay Relative to 1/fDATA_IQ)

DEC_MODE

Decimation

Factor

JESD204B

Lanes

IQ Data Output

Sample Delay

34.2

32.3

AD6676EBZ датащи(PDF) 40 Page - Analog Devices

AD6676EBZ датащи(HTML) 40 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

датащи скачать

ссылки URL