AD6676EBZ datasheet(55/90 Pages) AD

55 / 90 page

Data Sheet

AD6676

Rev. A | Page 55 of 90

used. Note that a differential clock source can also be ac coupled to

the CLK± pins while still meeting the minimum voltage swing

at the CLK+ input.

When the clock synthesizer is disabled, the CLK± inputs are

connected to a high-speed differential clock receiver with on-chip

100 Ω termination to simplify interfacing to CML, LVPECL, or

sinusoidal clock sources. The clock signal is typically ac-coupled to

the CLK+ and CLK− pins via a RF balun or capacitors. These

pins are biased internally (see Figure 60) at approximately 700 mV

and require no external bias. The equivalent shunt impedance of

the CLK± input is shown in Figure 131. It is recommended to

use a 100 Ω differential transmission line to route the clock signal

to the CLK+ and CLK− pins due to the high frequency nature

of the signal.

130

100

110

120

1.0

–0.4

–0.2

0.2

0.4

0.6

0.8

2.0

2.5

3.5

4.0

3.0

FREQUENCY (GHz)

REAL SHUNT

CAPACITANCE SHUNT

Figure 131. Equivalent Shunt Differential Input Impedance of the CLK± Pins

with the Clock Synthesizer Disabled

Figure 132 shows a single-ended clock solution for the AD6676

when its clock synthesizer is disabled. The low phase noise single-

ended source can be from an external VCXO. A ceramic RF chip

1:2 ratio balun creates the differential clock input signal. The

balun must be specified to have low loss (that is, less than 2 dB)

at the clock frequency of interest. The single-ended clock source

must be capable of 0 dBm drive capability to ensure adequate

signal swing into the clock input.

AD6676

CLK+

CLK–

CLOCK

INPUT

100pF

JT 4000BL14100

Figure 132. Balun-Coupled Differential Clock

A single-ended CMOS or differential ac-coupled PECL/HSTL

clock signal can be delivered via clock generation and distribution

ICs such as the Analog Devices HMC7044, AD9528, and

ADCLK925. A PECL clock signal is recommended when

providing a RF clock input signal to the AD6676 or in applications

that require deterministic latency or synchronization while using

the internal clock synthesizer of the AD6676. Figure 133 shows

a simple differential interface in which the AD6676 interfaces to

the PECL output available from these ICs. The HMC7044 is an

excellent choice for JESD204B clock generation and multichip

synchronization because it also generates a very low phase noise

RF clock from 2.4 GHz to 3.2 GHz for multiple AD6676 devices.

AD6676

CLK+

CLK–

10nF

240Ω

PECL

DRIVER

10nF

HMC7044,

AD9528 OR

ADCLK925

Figure 133. Differential PECL Sample Clock Using the HMC7044, AD9528, and

ADCLK925

Alternatively, PLL clock synthesizers with on-chip VCOs such

as the ADF4351, the ADF4355-2, and HMC1034 also make

excellent RF clock sources when multichip synchronization is

not required. The CML outputs of these devices allow a simple

interface as shown in Figure 134. Figure 135 compares the close

in phase noise between the ADF4351, the ADF4355-2, the

HMC7044, the AD6676 clock synthesizer, and the R&S SMA100A

for a near full-scale sine wave at 300 MHz. Note that the phase

noise improvement offered by the high quality RF generator

only becomes evident below 400 kHz when compared to the

ADF4351.

CLK+

CLK–

REFOUTA+

REFOUTA–

REFOUTB+

REFOUTB–

1nF

ADF4351

ADF4355-2

3.9nH

AD6676

0.8V p-p

PLL

VCO

FREF

VVCO

Figure 134. Differential CML Driver from the ADF4351 and the ADF4355

–110

–115

–120

–125

–130

–135

–140

–145

–150

–155

0.01

0.1

FREQUENCY OFFSET (MHz)

AD6676 CLK SYN

ADF4351

ADF4355-2

HMC7044

R&S SMA100A

AVG = 300

Figure 135. Close In Phase Noise Comparison for Different Analog Devices

Clock Sources when Compared to the R&S SMA100A and the AD6676 Clock

Synthesizer (IF = 300 MHz, BW = 40 MHz, FADC = 3.2 GHz, L = 19 nH)

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