AD6676EBZ datasheet(51/90 Pages) AD

51 / 90 page

Data Sheet

AD6676

Rev. A | Page 51 of 90

SYNCHRONIZATION USING SYSREF±

The AD6676 uses the SYSREF± input to provide synchronization

for the JESD204B serial output and to establish a fixed phase

reference for the decimation filters and the NCO within the QDDC.

Synchronization options are configurable via Register 0x1E8.

When initially synchronizing, the absolute phase offset relative

to the input clock applied to the CLK± pins depends on internal

clock phases and therefore has an uncertainty of ±1 ADC clock

cycles.

A clock tree diagram is shown in Figure 126 with an internal

clock signal, DIG_CLK, used to ultimately sample the SYSREF±

signal. Note that the SYSREF± setup and hold times are defined

with respect to the rising SYSREF± edge and rising CLK± (or

CLK+ with the clock synthesizer disabled) edge, as shown in

Figure 2. After the SYSREF± signal is sampled, the phase remains

locked to the same relative internal ADC_CLK phase offset

until the AD6676 is intentionally reset or its clock or power

interrupted.

Note the following considerations when using SYSREF± for

synchronization.

•

The SYSREF± pulse width must be at least two ADC_CLK

periods.

•

Bit 3 of Register 0x2BB must be set low when synchronizing

with the clock synthesizer enabled. In this case, that SYSREF±

is sampled on the rising edge of REF_CLK to allow for

significant margin in setup and hold time. This

synchronization signal is then sampled again with the

internally generated DIG_CLK.

•

Because SYSREF± is ultimately sampled with an internal

clock greater than 1 GHz, it can be difficult to maintain

synchronization of the clock and SYSREF± distribution in

a system over supply and temperature variations, as well

cumulative jitter affects. For this reason, it is suggested to

utilize the one shot SYSREF± mode to avoid unnecessary

resetting of the JES204B link.

•

If continuous SYSREF± is still preferred, it is recommended to

use the SYSREF_WIN_NEG and SYSREF_WIN_POS bits

in Register 0x1EA to allow for slight variation in SYSREF±

timing relative to DIG_CLK.

•

A phase variance of ±1 ADC clock cycles ultimately results

in fractions of a sample when referenced to the IQ output

data rate, fDATA_IQ, depending on the decimation factor. For

example, for a decimation factor of 32, the phase uncertainty

is expressed as ±1/32 samples relative to fDATA_IQ.

•

The course and fine digital NCOs are also set to an initial

phase up defined in Register 0x143 thru Register 0x145

upon receiving SYSREF±.

•

Figure 127 shows how the HMC7044 (or the AD9528) can

be used for mulichip synchronization. The HMC7044 is best

suited for delivering a low phase noise RF clock source for

each AD6676 (refer to Figure 135). In addition, its ability

to individually control the delays of both the CLK and

SYSREF signals to each AD6676 device allows

compensation of PCB skew delays.

CLOCK

SYNTHESIZER

fOUT =

5.9GHz TO 6.4GHz

÷2

CLK±

SYSREF±

RF_CLK

REG 0x2A5

ADC_CLK

DIG_CLK

Σ-Δ ADC

AND DIGITAL

TO DIGITAL

TO SYNCHRONIZATION

CIRCUITRY

REG 0x2BB

REF_CLK

÷2

Figure 126. Block Diagram Showing Options of Sampling the SYSREF Input Signal with the Clock Synthesizer Disabled or Enabled

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