GS6151 datasheet(58/77 Pages) SEMTECH

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GS6151

Final Data Sheet

Rev.4

PDS-060389

August 2015

58 of 77

Semtech

Proprietary & Confidential

www.semtech.com

22h

PRBS_GEN_CTRL

PRBSGEN_DATASEL

14:14

Determines the DFT data output.

00b: Clock

01b: PRBS7 data

PRBSGEN_DIV

13:12

Divide ratio for the DFT clock.

00b: divide by 1

01b: divide by 2

10b: divide by 4

11b: divide by 8

PRBSGEN_START

11:11

When toggled HIGH then LOW starts the

internal PRBS7 data source.

PRBSGEN_EXT_CLK

10:10

Selects the source for the DFT clock:

00b: Internally generated clock

01b: External clock

PRBSGEN_PHASE

9:8

Controls the phase of the internally

generated DFT clock.

00b: 0 degree phase

01b: 90 degree phase

10b: 180 degree phase

11b: 270 degree phase

PRBSGEN_CLKSEL

7:7

Determines the source clock used by the

PRBS generator when PRBSGEN_EXT = 0

(internally generated clock).

00b: DFT VCO clock

01b: CDR clock

PRBSGEN_RATESEL

6:2

One-hot encoded rate indicator for the

dividers in PRBS generator circuit.

00001b: MADI

00010b: SD

00100b: HD

01000b: 3G

10000b: 6G

PRBSGEN_VCO_

POWERDOWN

1:1

When HIGH, causes the open-loop PRBSGEN

VCO to be shut off even if PRBSGEN_ENABLE

= 1.

Has no effect when PRBSGEN_ENABLE = 0.

PRBSGEN_ENABLE

0:0

When HIGH, the PRBS7 generator circuit is

enabled.

Must be enabled when using any feature in

the PRBS_GEN_CTRL register.

Table 5-1: Register Descriptions - Standard Address Space (Continued)

Address Register Name

Parameter Name

Bit

Slice

R/W

Reset

Value

Description

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