 |
поискавой системы для электроныых деталей |
|
|
поискавой системы для электроныых деталей |
|
MEC1322 датащи(PDF) 174 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
MEC1322 датащи(HTML) 174 Page - Microchip Technology |
|
|
174 / 456 page  MEC1322 DS00001719D-page 174 2014 - 2015 Microchip Technology Inc. 13.11.1 POWER MANAGEMENT 1 STATUS 1 REGISTER 13.11.2 POWER MANAGEMENT 1 STATUS 2 REGISTER Note 13-1 These bits are set/cleared by the EC directly i.e., writing ‘1’ sets the bit and writing ‘0’ clears it. These bits can also be cleared by the Host software writing a one to this bit position and by VCC1_RESET. Writing a 0 by the Host has no effect. 13.11.3 POWER MANAGEMENT 1 ENABLE 1 REGISTER 06h Power Management 2 Control 1 Register 07h Power Management 2 Control 2 Register Offset 00h Bits Description Type Default Reset Event 7:0 Reserved R - - Offset 01h Bits Description Type Default Reset Event 7 WAK_STS This bit can be set or cleared by the EC. The Host writing a one to this bit can also clear this bit. R/WC (Note 13 -1) 00h VCC1_R ESET 6:4 Reserved R - - 3 PWRBTNOR_STS This bit can be set or cleared by the EC to simulate a Power button override event status if the power is controlled by the EC. The Host writing a one to this bit can also clear this bit. The EC must generate the associated hardware event under software control. R/WC (Note 13 -1) 00h VCC1_R ESET 2 RTC_STS This bit can be set or cleared by the EC to simulate a RTC status. The Host writing a one to this bit can also clear this bit. The EC must generate the associated SCI interrupt under software control. R/WC (Note 13 -1) 00h VCC1_R ESET 1 SLPBTN_STS This bit can be set or cleared by the EC to simulate a Sleep button status if the sleep state is controlled by the EC. The Host writing a one to this bit can also clear this bit. The EC must generate the associated SCI interrupt under software control. R/WC (Note 13 -1) 00h VCC1_R ESET 0 PWRBTN_STS This bit can be set or cleared by the EC to simulate a Power button status if the power is controlled by the EC. The Host writing a one to this bit can also clear this bit. The EC must generate the associated SCI interrupt under software control. R/WC (Note 13 -1) 00h VCC1_R ESET Offset 02h Bits Description Type Default Reset Event 7:0 Reserved R - - TABLE 13-7: RUNTIME REGISTERS SUMMARY (CONTINUED) Offset Register Name |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
