MEC1322 datasheet(291/456 Pages) MICROCHIP

291 / 456 page

 2014 - 2015 Microchip Technology Inc.

DS00001719D-page 291

MEC1322

26.5

Power, Clocks and Reset

This section defines the Power, Clock, and Reset parameters of the block.

26.5.1

POWER DOMAINS

26.5.2

CLOCK INPUTS

26.5.3

RESETS

26.6

Interrupts

This section defines the Interrupt Sources generated from this block.

26.7

Low Power Modes

The RPM-PWM Interface may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR) circuitry.

26.8

Description

This section defines the functionality of the block.

26.8.1

GENERAL OPERATION

The RPM-PWM Interface is an RPM based Fan Control Algorithm that monitors the fan’s speed and automatically

adjusts the drive to maintain the desired fan speed. This RPM based Fan Control Algorithm controls a PWM output

based on a tachometer input.

26.8.2

FAN CONTROL MODES OF OPERATION

The RPM-PWM Interface has two modes of operation for the PWM Fan Driver. They are:

Manual Mode - in this mode of operation, the user directly controls the fan drive setting. Updating the Fan Driver

Setting Register (see Section 26.9.1, "Fan Setting Register") will update the fan drive based on the programmed

ramp rate (default disabled).

• The Manual Mode is enabled by clearing the EN_ALGO bit in the Fan Configuration Register (see Section 26.9.3,

"Fan Configuration 1 Register").

• Whenever the Manual Mode is enabled the current drive settings will be changed to what was last used by the

RPM control algorithm.

• Setting the drive value to 00h will disable the PWM Fan Driver.

• Changing the drive value from 00h will invoke the Spin Up Routine.

TABLE 26-2:

POWER SOURCES

Name

Description

VCC1

This power well sources the registers and logic in this block.

TABLE 26-3:

CLOCK INPUTS

Name

Description

48 MHz Ring Oscillator

This clock signal drives selected logic (e.g., counters).

TABLE 26-4:

RESET SIGNALS

Name

Description

VCC1_RESET

This reset signal resets all of the registers and logic in this block.

TABLE 26-5:

INTERRUPTS

Source

Description

Fan Fail/Spin Status Interrupt

The DRIVE_FAIL & FAN_SPIN bits in the Fan Status Register are logi-

cally ORed and routed to the FAIL_SPIN Interrupt

Fan Stall Status Interrupt

The FAN_STALL bit in the Fan Status Register is routed to the

FAN_STALL Interrupt

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