MEC1322 datasheet(280/456 Pages) MICROCHIP

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MEC1322

DS00001719D-page 280

 2014 - 2015 Microchip Technology Inc.

24.10.1

MODES OF OPERATION

The Tachometer block supports two modes of operation. The mode of operation is selected via the TACH_READING_-

MODE_SELECT bit.

24.10.1.1

Free Running Counter

In Mode 0, the Tachometer block uses the TACH input as the clock source for the internal TACH pulse counter (see

TACHX_COUNTER). The counter is incremented when it detects a rising edge on the TACH input. In this mode, the

firmware may periodically poll the TACHX_COUNTER field to determine the average speed over a period of time. The

firmware must store the previous reading and the current reading to compute the number of pulses detected over a

period of time. In this mode, the counter continuously increments until it reaches FFFFh. It then wraps back to 0000h

and continues counting. The firmware must ensure that the sample rate is greater than the time it takes for the counter

to wrap back to the starting point.

24.10.1.2

Mode 1 -- Number of Clock Pulses per Revolution

In Mode 1, the Tachometer block uses its 100kHz_Clk clock input to measure the programmable number of TACH

pulses. In this mode, the internal TACH pulse counter (TACHX_COUNTER) returns the value in number of 100kHz_Clk

pulses per programmed number of TACH_EDGES. For fans that generate two square waves per revolution, these bits

should be configured to five edges.

When the number of edges is detected, the counter is latched and the COUNT_READY_STATUS bit is asserted. If the

COUNT_READY_INT_EN bit is set a TACH interrupt event will be generated.

24.10.2

OUT-OF-LIMIT EVENTS

The TACH Block has a pair of limit registers that may be configured to generate an event if the Tach indicates that the

fan is operating too slow or too fast. If the <TACH reading> exceeds one of the programmed limits, the TACHx High

Limit Register and the TACHx Low Limit Register, the bit TACH_OUT_OF_LIMIT_STATUS will be set. If the

TACH_OUT_OF_LIMIT_STATUS bit is set, the Tachometer block will generate an interrupt event.

24.11 EC-Only Registers

The registers listed in the EC-Only Register Summary table are for a single instance of the TACH. The addresses of

each register listed in this table are defined as a relative offset to the host “Base Address” defined in the EC-Only Reg-

ister Base Address Table.

The Base Address indicates where the first register can be accessed in a particular address space for a block instance.

Note:

Tach interrupts should be disabled in Mode 0.

TABLE 24-2:

EC-ONLY REGISTER BASE ADDRESS TABLE

Block Instance

Instance

Number

Host

Address Space

Base Address

TACH

32-bit internal

address space

4000_6000h

TACH

32-bit internal

address space

4000_6010h

TABLE 24-3:

TACH REGISTER SUMMARY

Offset

00h

TACHx Control Register

04h

TACHx Status Register

08h

TACHx High Limit Register

0Ch

TACHx Low Limit Register

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