Data Sheet

ADF5355

Rev. A | Page 33 of 38

Figure 53. Register 12

REGISTER 12

Control Bits

With Bits[C4:C1] set to 1100, Register 12 is programmed.

Figure 53 shows the input data format for programming this

register.

Phase Resync Clock Divider Value

P16 to P1 (Bits[DB31:DB16]) set the timeout counter for

activation of phase resync. This value must be set such that

a resync happens immediately after (and not before) the PLL

has achieved lock after reprogramming.

Calculate the timeout value using the following equation:

When not using phase resync, set these bits to 1 for normal

operation.

Reserved

Bits[DB15:DB4] are reserved. Bit DB10 and Bit DB4 must be set

to 1, and all other bits in this range must be set to 0.

REGISTER INITIALIZATION SEQUENCE

At initial power-up, after the correct application of voltages to

the supply pins, program the ADF5355 registers in the

following sequence:

1.

Register 12

2.

Register 11

3.

Register 10

4.

Register 9

5.

Register 8

6.

Register 7

7.

Register 6

8.

Register 5

9.

Register 4

10. Register 3

11. Register 2

12. Register 1

13. Register 0

FREQUENCY UPDATE SEQUENCE

Frequency updates require updating the auxiliary modulator

(MOD2) in Register 2, the fractional value (FRAC1) in Register 1,

and the integer value (INT) in Register 0. Toggling the counter

reset bit (Register 4) is also required. Therefore, the update

sequence must be as follows:

1.

Register 4 (counter reset enabled (DB4 = 1)).

2.

Register 2 (new FRAC2 and MOD2).

3.

Register 1 (new FRAC1).

4.

Register 0 (new INT and AUTOCAL disabled (DB21 = 0)).

5.

Register 4 (counter reset disabled (DB4 = 0)).

6.

Wait >16 ADC_CLK cycles. For example, if ADC_CLK =

99.417 kHz, wait 16/99417 sec = 161 μs. See Register 10.

7.

Register 0 (new INT and AUTOCAL enabled (DB21 = 1)).

The frequency change occurs on the second write to Register 0.

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

P13

P12

P11

P10

P9

PHASE RESYNC CLOCK DIVIDER

CONTROL

BITS

P8

P7

P6

P5

P4

P3

P2

P1

0

0

0

0010000

0

1

C3(1) C2(0) C1(0)

C4(1)

P14

P15

P16

P16

P15

...

P5

P4

P3

P2

P1

PHASE RESYNC CLOCK DIVIDER

00

...

00

000

NOT ALLOWED

00

...

00

001

1/NORMAL OPERATION

00

...

00

010

2

.

.

...

.

.

.

.

.

...

00

...

10

110

22

00

...

10

111

23

00

...

11

000

24

.

.

...

.

.

.

.

.

...

11

...

11

101

65533

11

...

11

110

65534

11

...

11

111

65535

RESERVED