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Data Sheet

ADF5355

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

CLK

Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high

impedance CMOS input.

DATA

Serial Data Input. The serial data is loaded most significant bit (MSB) first with the four least significant bits

(LSBs) as the control bits. This input is a high impedance CMOS input.

Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register

that is selected by the four LSBs.

Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode.

A logic high (at levels equal to DVDD) on this pin powers up the device, depending on the status of the power-

down bits.

5, 16

AVDD

Analog Power Supply. This pin ranges from 3.15 V to 3.45 V. Connect decoupling capacitors to the analog

ground plane as close to this pin as possible. AVDD must have the same value as DVDD.

Charge Pump Power Supply. VP must have the same value as VVCO. Connect decoupling capacitors to the

ground plane as close to this pin as possible.

CPOUT

Charge Pump Output. When enabled, this output provides ±ICP to the external loop filter. The output of the

loop filter is connected to VTUNE to drive the internal VCO.

CPGND

Charge Pump Ground. This output is the ground return pin for CPOUT.

AGND

Analog Ground. Ground return pin for AVDD.

VRF

Power Supply for the RF Output. Connect decoupling capacitors to the analog ground plane as close to this

pin as possible. VRF must have the same value as AVDD.

RFOUTA+

VCO Output. The output level is programmable. The VCO fundamental output or a divided down version is

available. This pin can be left floating if RFOUTA is disabled in Register 6 or by the PDBRF pin.

RFOUTA−

Complementary VCO Output. The output level is programmable. The VCO fundamental output or a divided

down version is available. This pin can be left floating if RFOUTA is disabled in Register 6 or by the PDBRF pin.

13, 15

AGNDRF

RF Output Stage Ground. Ground return pins for the RF output stage.

RFOUTB

Auxiliary VCO Output. The 2× VCO output is available at this pin.

VVCO

Power Supply for the VCO. The voltage on this pin ranges from 4.75 V to 5.25 V. Place decoupling capacitors to

the analog ground plane as close to this pin as possible. For best performance, this supply must be clean and

have low noise.

18, 21

AGNDVCO

VCO Ground. Ground return path for the VCO.

VREGVCO

VCO Compensation Node. Place decoupling capacitors to the ground plane as close to this pin as possible.

Connect this pin directly to VVCO.

VTUNE

Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CPOUT

output voltage.

RSET

Bias Current Resistor. Connecting a resistor between this pin and ground sets the charge pump output current.

CLK

DATA

VBIAS

VREF

CPOUT

CPGND

RSET

VTUNE

AGNDVCO

VVCO

NOTES

1. THE EXPOSED PAD MUST BE CONNECTED TO AGND.

VREGVCO

AVDD

ADF5355

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