ADF5355

Data Sheet

Rev. A | Page 30 of 38

Figure 48. Register 7

REGISTER 7

Control Bits

With Bits[C4:C1] set to 0111, Register 7 is programmed. Figure 48

shows the input data format for programming this register.

Reserved

Bits[DB31:DB29] are reserved and must be set to 0. Bit DB28 is

reserved and must be set to 1. Bits[DB27:DB26] are reserved

and must be set to 0.

LE Sync

When set to 1, Bit DB25 ensures that the load enable (LE) edge

is synchronized internally with the rising edge of reference

input frequency. This synchronization prevents the rare event of

reference and RF dividers loading at the same time as a falling edge

of the reference frequency, which can lead to longer lock times.

Reserved

Bits[DB24:DB10] are reserved and must be set to 0.

Fractional-N Lock Detect Count (LDC)

LD5 and LD4 (Bits[DB9:DB8]) set the number of consecutive

cycles counted by the lock detect circuitry before asserting lock

detect high. See Figure 48 for details.

Loss of Lock (LOL) Mode

Set the LOL mode bit (Bit DB7) to 1 when the application is a

likely to be removed, such as a clocking application. The standard

this may not be the case with clocking applications. To enable this

functionality, set DB7 to 1.

Fractional-N Lock Detect Precision (LDP)

LD3 and LD2 (Bits[DB6:DB5]) set the precision of the lock detect

circuitry in fractional-N mode. LDP is available at 5 ns, 6 ns, 8 ns,

or 12 ns. If bleed currents are used, use 12 ns.

Lock Detect Mode (LDM)

If LD1 (Bit DB4) is set to 0, each reference cycle is set by

fractional-N lock detect precision as described in the

Fractional-N Lock Detect Count (LDC) section. If DB4 is

set to 1, each reference cycle is 2.9 ns long, which is more

appropriate for integer-N applications.

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3

DB2

DB1

DB0

0

0

LE

0

0

0000000

0

LD1

C3(1) C2(1) C1(1)

CONTROL

BITS

RESERVED

LD3

LD2

FRACTIONAL-N LD PRECISION

0

0

5.0ns

0

1

6.0ns

1

0

8.0ns

1

1

12.0ns

LD1

0

FRACTIONAL-N

1

INTEGER-N (2.9ns)

C4(0)

LOCK DETECT MODE

LD2

LD3

LOL

0

DISABLED

1

ENABLED

LOSS OF LOCK MODE

LOL

LD5

LD4

LOCK DETECT CYCLE COUNT

0

0

1024

0

1

2048

1

0

4096

1

1

8192

LD4

LD5

LD

CYCLE

COUNT

0

0

0

0

0

0

1

0

0

LE

0

DISABLED

1

LE SYNCED TO REFIN

LE SYNCHRONIZATION

RESERVED