ADF5355 datasheet(16/38 Pages) AD

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ADF5355

Data Sheet

Rev. A | Page 16 of 38

CIRCUIT DESCRIPTION

REFERENCE INPUT

Figure 32 shows the reference input stage. The reference input

can accept both single-ended and differential signals. Use the

reference mode bit (Register 4, DB9) to select the signal. To use a

differential signal on the reference input, program this bit high.

In this case, SW1 and SW2 are open, SW3 and SW4 are closed,

and the current source that drives the differential pair of

transistors switches on (see Figure 32). The differential signal is

buffered, and it is provided to an emitter coupled logic (ECL) to

CMOS converter. When a single-ended signal is used as the

reference, connect the reference signal to REFINA and program

Bit DB9 in Register 4 to 0. In this case, SW1 and SW2 are

closed, SW3 and SW4 are open, and the current source that

drives the differential pair of transistors switches off.

Figure 32. Reference Input Stage, Differential Mode

RF N DIVIDER

The RF N divider allows a division ratio in the PLL feedback

path. Determine the division ratio by the INT, FRAC1, FRAC2,

and MOD2 values that this divider comprises.

Figure 33. RF N Divider

INT, FRAC, MOD, and R Counter Relationship

The INT, FRAC1, FRAC2, MOD1, and MOD2 values, in

conjunction with the R counter, make it possible to generate

output frequencies that are spaced by fractions of the PFD

frequency (fPFD). For more information, see the RF Synthesizer—

A Worked Example section.

Calculate the VCO output frequency (VCOOUT) by

VCOOUT = fPFD × N

(1)

where:

VCOOUT is the output frequency of the external VCO voltage

controlled oscillator (without using the output divider).

fPFD is the frequency of the phase frequency detector.

N is the desired value of the feedback counter, N.

Calculate fPFD by

fPFD = REFIN × [(1 + D)/(R × (1 + T))]

(2)

where:

REFIN is the reference input frequency.

D is the REFIN doubler bit.

R is the preset divide ratio of the binary 10-bit programmable

reference counter (1 to 1023).

T is the REFIN divide by 2 bit (0 or 1)

N comprises

MOD1

MOD2

FRAC2

FRAC1

INT





(3)

where:

INT is the 16-bit integer value (23 to 32,767 for 4/5 prescaler,

75 to 65,535 for 8/9 prescaler).

FRAC1 is the numerator of the primary modulus (0 to 16,777,215).

FRAC2 is the numerator of the 14-bit auxiliary modulus

(0 to 16,383).

MOD2 is the programmable, 14-bit auxiliary fractional

modulus (2 to 16,383).

MOD1 is a 24-bit primary modulus with a fixed value of 224 =

16,777,216.

This calculation results in a very fine frequency resolution with

no residual frequency error. To apply this formula, take the

following steps:

Calculate N by dividing VCOOUT/fPFD.

The integer value of this number forms INT.

Subtract this value from the full N value.

Multiply the remainder by 224.

The integer value of this number forms FRAC1.

Calculate MOD2 based on the channel spacing (fCHSP) by

MOD2 = fPFD/GCD(fPFD, fCHSP)

(4)

where:

fCHSP is the desired channel spacing frequency.

GCD

(fPFD, fCHSP) is the greatest common divisor of the PFD

frequency and the channel spacing frequency.

Calculate FRAC2 by the following equation:

FRAC2 = [(N − INT) × 224 − FRAC1)] × MOD2

(5)

2.5kΩ

REFINA

REFINB

AVDD

BIAS

GENERATOR

BUFFER

85kΩ

SW2

SW3

SW1

REFERENCE

INPUT MODE

SW4

ECL TO CMOS

BUFFER

R COUNTER

MULTIPLEXER

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

FRAC1

REG

INT

REG

RF N COUNTER

FROM

VCO OUTPUT/

OUTPUT DIVIDERS

TO PFD

N COUNTER

FRAC2

VALUE

MOD2

VALUE

N = INT +

FRAC1 +

MOD1

FRAC2

MOD2

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