XC164CS datasheet(28/71 Pages) INFINEON

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XC164

Derivatives

Functional Description

Data Sheet

V2.1, 2003-06

The XC164 also provides an excellent mechanism to identify and to process exceptions

or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware

traps cause immediate non-maskable system reaction which is similar to a standard

interrupt service (branching to a dedicated vector table location). The occurence of a

hardware trap is additionally signified by an individual bit in the trap flag register (TFR).

Except when another higher prioritized trap service is in progress, a hardware trap will

interrupt any actual program execution. In turn, hardware trap services can normally not

be interrupted by standard or PEC interrupts.

Table 5 shows all of the possible exceptions or error conditions that can arise during run-

time:

Table 5

Hardware Trap Summary

Exception Condition

Trap

Flag

Trap

Vector

Location1)

Trap

Number

Trap

Priority

Reset Functions:

– Hardware Reset

– Software Reset

– W-dog Timer Overflow

–

RESET

xx’0000H

00H

III

Class A Hardware Traps:

– Non-Maskable Interrupt

– Stack Overflow

– Stack Underflow

– Software Break

NMI

STKOF

STKUF

SOFTBRK

NMITRAP

STOTRAP

STUTRAP

SBRKTRAP

xx’0008H

xx’0010H

xx’0018H

xx’0020H

02H

04H

06H

08H

Class B Hardware Traps:

– Undefined Opcode

– PMI Access Error

– Protected Instruction

Fault

– Illegal Word Operand

Access

UNDOPC

PACER

PRTFLT

ILLOPA

BTRAP

xx’0028H

0AH

Reserved

–

[2CH –

3CH]

[0BH –

0FH]

–

Software Traps

– TRAP Instruction

––

Any

[xx’0000H –

xx’01FCH]

in steps

of 4H

Any

[00H –

7FH]

Current

CPU

Priority

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