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XC164CS датащи(PDF) 67 Page - Infineon Technologies AG

номер детали XC164CS
подробное описание детали  16-Bit Single-Chip Microcontroller
PDF  71 Pages
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производитель  INFINEON [Infineon Technologies AG]
домашняя страница  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

XC164CS датащи(HTML) 67 Page - Infineon Technologies AG

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XC164
Derivatives
Timing Parameters
Data Sheet
63
V2.1, 2003-06
Note: The shaded parameters have been verified by characterization.
They are not 100% tested.
Table 19
External Bus Cycle Timing (Operating Conditions apply)
Parameter
Symbol
Limits
Unit
min.
max.
Output valid delay for:
RD, WR(L/H)
tc10 CC 113
ns
Output valid delay for:
A23
…A16, BHE, ALE
tc11 CC -1
7
ns
Output valid delay for:
A15
…A0 (on PORT1)
tc12 CC 116
ns
Output valid delay for:
A15
…A0 (on PORT0)
tc13 CC 316
ns
Output valid delay for:
CS
tc14 CC 114
ns
Output valid delay for:
D15
…D0 (write data, mux-mode)
tc15 CC 317
ns
Output valid delay for:
D15
…D0 (write data, demux-mode)
tc16 CC 317
ns
Output hold time for:
RD, WR(L/H)
tc20 CC -3
3ns
Output hold time for:
A23
…A16, BHE, ALE
tc21 CC 0
8ns
Output hold time for:
A15
…A0 (on PORT0)
tc23 CC 1
13
ns
Output hold time for:
CS
tc24 CC -3
3ns
Output hold time for:
D15
…D0 (write data)
tc25 CC 1
13
ns
Input setup time for:
READY, D15
…D0 (read data)
tc30 SR 24
–
ns
Input hold time
READY, D15
…D0 (read data)1)
tc31 SR -5
–
ns
1)
Read data are latched with the same (internal) clock edge that triggers the address change and the rising edge
of RD. Therefore address changes before the end of RD have no impact on (demultiplexed) read cycles. Read
data can be removed after the rising edge of RD.



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