XC164CS datasheet(19/71 Pages) INFINEON

19 / 71 page

XC164

Derivatives

Functional Description

Data Sheet

V2.1, 2003-06

3.1

Memory Subsystem and Organization

The memory space of the XC164 is configured in a Von Neumann architecture, which

means that all internal and external resources, such as code memory, data memory,

registers and I/O ports, are organized within the same linear address space. This

common memory space includes 16 Mbytes and is arranged as 256 segments of

64 Kbytes each, where each segment consists of four data pages of 16 Kbytes each.

The entire memory space can be accessed bytewise or wordwise. Portions of the on-

chip DPRAM and the register spaces (E/SFR) have additionally been made directly

bitaddressable.

The internal data memory areas and the Special Function Register areas (SFR and

ESFR) are mapped into segment 0, the system segment.

The Program Management Unit (PMU) handles all code fetches and, therefore, controls

accesses to the program memories, such as Flash memory, ROM, and PSRAM.

The Data Management Unit (DMU) handles all data transfers and, therefore, controls

accesses to the DSRAM and the on-chip peripherals.

Both units (PMU and DMU) are connected via the high-speed system bus to exchange

data. This is required if operands are read from program memory, code or data is written

to the PSRAM, code is fetched from external memory, or data is read from or written to

external resources, including peripherals on the LXbus (such as TwinCAN). The system

bus allows concurrent two-way communication for maximum transfer performance.

128 Kbytes of on-chip Flash memory or mask-programmable ROM store code or

constant data. The on-chip Flash memory is organized as four 8-Kbyte sectors, one

32-Kbyte sector, and one 64-Kbyte sector. Each sector can be separately write

protected1), erased and programmed (in blocks of 128 Bytes). The complete Flash or

ROM area can be read-protected. A password sequence temporarily unlocks protected

areas. The Flash module combines very fast 64-bit one-cycle read accesses with

protected and efficient writing algorithms for programming and erasing. Thus, program

execution out of the internal Flash results in maximum performance. Dynamic error

correction provides extremely high read data security for all read accesses.

Programming typically takes 2 ms per 128-byte block (5 ms max.), erasing a sector

typically takes 200 ms (500 ms max.).

2 Kbytes of on-chip Program SRAM (PSRAM) are provided to store user code or data.

The PSRAM is accessed via the PMU and is therefore optimized for code fetches.

2 Kbytes of on-chip Data SRAM (DSRAM) are provided as a storage for general user

data.The DSRAM is accessed via the DMU and is therefore optimized for data accesses.

2 Kbytes of on-chip Dual-Port RAM (DPRAM) are provided as a storage for user

defined variables, for the system stack, general purpose register banks. A register bank

can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, …, RL7, RH7)

Each two 8-Kbyte sectors are combined for write-protection purposes.

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