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SM5906AF датащи(PDF) 20 Page - Nippon Precision Circuits Inc |
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SM5906AF датащи(HTML) 20 Page - Nippon Precision Circuits Inc |
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20 / 30 page ![]() NIPPON PRECISION CIRCUITS-20 SM5906AF 85H (option settings) – RAMSEL When 0 : 4M DRAMs (1M ×4 bits) When 1 : 16M DRAMs (4M ×4 bits) – YFLGS When 0 : Sets FLAG6 when YFLAG=0 When 1 : Sets FLAG6 when YFLAG=1 – IBSEL2, IBSEL1 When 0 and 1 : Input bit clock(YSCK)=16-bit mode When 1 and 1 : Input bit clock(YSCK)=32-bit mode In all other cases: Input bit clock(YSCK)=24-bit mode Changing mode without initializing during opera- tion is possible. – CDMODE2, CDMODE1 When 0 and 0 : CDDA mode YSRDATA only is stored as data in DRAM, with output data on ZSRDATA. When 1 and 0 : SVC mode YSRDATA and YC2PO are stored as data in DRAM, with output data at double speed if MSON = 1 only (CD-DA mode if MSON = 0). In all other cases: VCD mode YSRDATA and YC2PO are stored as data in DRAM, with output data on ZSRDATA and ZC2PO. Changing mode without initializing during opera- tion is possible. 83H ( NMSOFF, MUTE, REFRESH, SCOFF settings) – NMSOFF (new through mode) When 1: Input signals YSCK, YSRDATA, YLRCK, YC2PO are connected directly to outputs ZSCK, ZSRDATA, ZLRCK, ZC2PO as is. When 0: No operation – MUTE (forced muting) When 1: Outputs are instantaneously muted to 0. (note 1) Same effect as taking the YDMUTE pin HIGH. When 0: No muting (note 1) (note1) Effective at the start of left-channel output data. – MUTE, YDMUTE relationship When all mute inputs are 0, mute is released. – REFRESH (refresh mode) When 1: During momentary pause in shock-proof mode operation, DRAM is accessed in a refresh cycle to maintain data written to DRAM. When 0: No operation – SCOFF (SYNC counter off) A sync counter is used to count 588 data sam- ples per sync cycle. The counter starts when sync data is detected, and valid data is updated after each cycle if sync data is verified. If sync data is not detected, the SYNCWAR and SYNCER flags are set. When 1: The counter is off (sync cycle is not involved) and valid data is updated when the sync data is detected and verified. When 0: Counts the sync cycles, and updates valid data. |
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