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SM5906AF датащи(PDF) 18 Page - Nippon Precision Circuits Inc |
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SM5906AF датащи(HTML) 18 Page - Nippon Precision Circuits Inc |
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18 / 30 page ![]() NIPPON PRECISION CIRCUITS-18 SM5906AF Flag Read name method MSRIH READ Meaning – Indicates that the read sequence has stopped due to internal factors 90H (not microcontroller commands) bit 1 Set – When the valid data residual becomes 0 Reset – By 90H status read – When a read address clear (MSRACL) or write address clear (MSWACL) command is recieved – After external reset SYNCWAR READ Meaning – Indicates residual is not updated because sync data not verified for 1 block 90H Set – When sync data is not verified for 1 block (C2PO error etc.) bit 0 – When sync data does not occur within a 2352-byte interval Reset – By 90H status read – After external reset – When MSWACL, MSRACL are issued MSEMP READ Meaning – Indicates that the valid data residual has become 0 91H Set – When the VWA (final valid data's next address) bit 7 = RA (address from which the next read would take place) Reset – Whenever the above does not apply OVFL READ Meaning – Indicates a write to external DRAM overflow state 91H Set – When the write address (WA) exceeds the read address (RA). bit 6 (Note: This flag is not set when WA=RA through an address initialize or reset operation.) Reset – When the read address (RA) is advanced by the read sequence – When a read address clear (MSRACL) or write address clear (MSWACL) command is issued – After external reset WRSQ READ Meaning – Indicates that the write sequence (input data entry, DRAM write) is operating 91H Set – By the 80H command when MSWREN=1 bit 5 – When conforming data is detected during compare-connect operation – When the connect has been performed after receiving a direct connect command Reset – When the FLAG6 flag=1 (above) – When the OVFL flag=1 (above) – When the BOVF flag=1 (above) – By the 80H command when MSWREN=0 – By the 80H command when MSDCN1=1 or MSDCN2=1 (compare-connect start command) – By the 80H command when MSON=0 – After external reset Note. Reset conditions have priority over set conditions. However, simultaneous MSWREN = 1 and compare-connect operation has precedence over WRSQ. RDSQ READ Meaning – Indicates that the read sequence (read from DRAM, data output) is operating 91H Set – By a new 80H command when MSRDEN=1 and the MSEMP flag=0 (above) bit 4 Reset – Whenever the above does not apply |
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