ML2721 datasheet(22/27 Pages) MICRO-LINEAR

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ML2721

January, 2000

PRELIMINARY DATASHEET

PRELIMINARY

TRANSMIT AND RECEIVE DATA

INTERFACES

The DIN and DOUT pins are CMOS logic level for serial

data that correspond to FSK modulation on the radio

channel. The ML2721 is designed to operate as an FSK

transceiver in the 902 to 928MHz ISM band. The chip

rate, bit rate and spreading code are determined in the

baseband processor, and the FM deviation and transmit

filtering are determined in the transceiver.

DIN provides data to the Transmit data filter, which band

limits the transmitted chips before they are FM

modulated. There is no re-timing of the chips, so the

transmitted FSK chips take their timing from the DIN pin.

In the Receive chain FM demodulation, data filtering,

and data slicing take place in the ML2721 receiver, with

chip, bit and word rate timing recovery performed in the

baseband processor.

RSSI, LD, AND REF

There are three other interface pins between the ML2721

transceiver and the baseband IC: the RSSI, LD and REF

pins.

REF is the master reference frequency for the transceiver.

It supplies the frequency reference for the RF channel

frequency and the filter tuning. The REF pin is a CMOS

input with internal biasing resistors. It can be AC coupled

through a 470pF coupling capacitor to a sine wave source

of between 0.5 and 3.0V peak-to-peak. The REF input can

also be driven by a CMOS logic output. The PLL

comparison and the IF filter center frequency are both

equal to the REF input frequency divided by either 6 or

12, depending on the setting of the RDIV bit in the PLL

configuration control word. The IF filter and data filter

bandwidths track the IF filter center frequency.

The Received Signal Strength Indicator (RSSI) pin supplies

a voltage indicating the amplitude of the received RF

signal. It is normally connected to the input of a low

speed ADC on an external baseband IC, and is used

during channel scanning to detect clear channels on

which the radio may transmit. The RSSI voltage is

proportional to the logarithm of the received power level.

A voltage of 0V to 2.7V corresponds to an RF input power

of –95 to –15dBm with a nominal slope of 33mV/dB.

The Lock Detect (LD) pin is an open drain output that

pulses low when the PLL is in frequency lock. It is

provided to indicate to an external baseband processor

that the ML2721 PLL is failing to lock to the reference

frequency. This output is latched on the falling edge of

PLLEN. The baseband processor can sample LD after de-

asserting PLLEN.

In analog test modes the RSSI and LD pins become analog

test access ports (TPI and TPQ, respectively) that allow

the user to observe internal signals in the ML2721.

RF INTERFACES

The RRFI receive input pin and the TRFO transmit output

pin are the only RF I/O pins and provide approximately

W impedance. The RRFI pin requires a simple input

matching network for best input noise figure, and the

TRFO pin is matched to 50

W by an AC coupling

capacitor. The application circuit shows recommended

matching circuit values for the Micro Linear

demonstration PCB, but different values will be needed for

other PCB layouts. The associated RF input and output

ground pins must have direct connections to an RF ground

plane, and the RF block supply pins must be well

decoupled from the RF ground pins.

CONTROL INTERFACE (CONTINUED)

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