ML2721 datasheet(20/27 Pages) MICRO-LINEAR

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ML2721

January, 2000

PRELIMINARY DATASHEET

PRELIMINARY

Table 14. PLL Frequency Shift

Table 12. Analog Test Control Bits

Table 13. Digital Test Control Bits

Table 11. Main Divider

CONTROL REGISTER BIT DESCRIPTIONS

ADR<1:0>, All 4 Registers

Address bits for all registers. The ADR<1:0> bits are the

LSB of each register. Each register is divided into data

field and address field. The data field is the leading field,

while the last two bits clocked into the register are always

the address field. The address field is decoded and the

addressed destination register loaded when EN goes high.

The last 16 bits clocked into the serial bus will be loaded

into the register. Clocking in less than 16-bits will result in

potentially incorrect entry into the register.

ATM<2:0>, Register #2 Only

Analog test control bits. The test mode selected is

described in Table 12. The performance of the ML2721 is

not guaranteed in these test modes. Although primarily

intended for IC test and debug, they can also help in

debugging the radio system. The default (power up) state

of these bits is ATM<2:0> = <0,0,0>. When a non-zero

value is written to the field, the RSSI and LD pins become

analog test access ports giving access to the outputs of

key signal processing stages in the transceiver. During

normal operation the ATM field should be set to zero.

DTM <2:0>, Register #2 Only

Digital test control bits. The DTM<2:0> bits function is

described in Table 13. The performance of the ML2721 is

not guaranteed in these test modes. Although primarily

intended for IC test and debug, they can also help in

debugging the radio system. The default (power up) state

of these bits is DTM<2:0> = <0,0,0>. When a non-zero

value is written to these fields the DOUT pin becomes a

digital test access port for key digital signals in the

transceiver. During normal operation the DTM field should

be set to zero.

CHQ <11:0>, Register #1 Only

Channel frequency selection bits. These bits set the

channel frequency for the transceiver. With a 6.144MHz

or 12.288MHz input to the REF pin the channel frequency

value is calculated by dividing the CHQ value by 0.512.

A 1.024MHz offset is automatically added in the receiver

mode to accommodate the IF frequency. The

recommended operating range value of the CHQ is from

1,024 (400hex) to 4,094 (FFEhex). These bits should be

programmed to a valid channel frequency before XCEN is

asserted.

LOL Register #0 Only

PLL frequency shift bit. LO shift for transmit and receive.

For normal operations, it is recommended that LOL = 0.

See Table 14.

CONTROL INTERFACES AND REGISTER DESCRIPTION (continued)

Power On State

All the registers are cleared when voltage is applied to

VDD (pin 31). The PLL divide ratio (See Table 11) and PLL

configuration registers should be programmed before

XCEN is asserted for the first time. The divide ratio is

calculated as fC/0.512 where fC is the channel frequency

in MHz.

Divide Ratio =

0.512

A 1.024MHz offset is automatically added in the Receive

mode.

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