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ML2721 датащи(PDF) 14 Page - Micro Linear Corporation

номер детали ML2721
подробное описание детали  Low IF Digital Cordless Transceiver
PDF  27 Pages
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производитель  MICRO-LINEAR [Micro Linear Corporation]
домашняя страница  http://www.microlinear.com
Logo MICRO-LINEAR - Micro Linear Corporation

ML2721 датащи(HTML) 14 Page - Micro Linear Corporation

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ML2721
14
January, 2000
PRELIMINARY DATASHEET
PRELIMINARY
Figure 8. Phase Locked Loop in Receive Mode
Table 6. Receive Mode Frequency Relationships
(N+2)
× FCOMP
N
× FCOMP/2
DIVIDER
ADDER
12
P D
FCOMP
REF
PLLEN
REGISTER 1
BIT14...BIT3
INPUT SIGNAL AT
N
× FCOMP/2
IF AT FCOMP
2
N
÷6 or
÷12
FCOMP
VCO
LOOP FILTER
÷2
circuits do not reprogram the PLL for every receive or
transmit packet. The PLL divide register should be
programmed with a binary integer which represents the
desired RF channel frequency divided by 0.512 MHz
(when using a 6.144 or 12.288MHz reference frequency).
When in TRANSMIT mode the PLL is disabled and the
loop opened to allow modulation of the VCO. The VCO
runs at twice the channel frequency, and the Transmit RF
output is taken from one output of the quadrature divider.
The PLL locks during TXCAL mode.
The frequency plan for the PLL and VCO transmit is given
in Table 5.
When in RECEIVE mode the PLL is disabled to conserve
power and prevent PLL divider noise from desensitizing
the receiver. See Figure 8. The PLL frequency is set to
give a LO frequency equal to the desired RF channel
frequency plus the IF frequency. The VCO signal is
divided by two to provide the quadrature LO for the
image reject down convert mixer. The PLL locks during
RXCAL mode.
Table 5. Transmit Mode Frequency Relationsships
MODE OF OPERATION (CONTINUED)
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