W97AH6KB datasheet(3/127 Pages) WINBOND

3 / 127 page

W97AH6KB / W97AH2KB

Publication Release Date: May 15, 2014

Revision: A01-001

- 3 -

7.4.22.1

Mode Register Write Timing Example: RL = 3, tMRW = 5 ................................................................................. 61

7.4.22.2

Truth Table for Mode Register Read (MRR) and Mode Register Write (MRW).................................................. 61

7.4.23

Mode Register Write Reset (MRW Reset) ................................................................................................................... 62

7.4.24

Mode Register Write ZQ Calibration Command ........................................................................................................... 62

7.4.24.1

ZQ Calibration Initialization Timing Example ..................................................................................................... 63

7.4.24.2

ZQ Calibration Short Timing Example ............................................................................................................... 63

7.4.24.3

ZQ Calibration Long Timing Example................................................................................................................ 64

7.4.24.4

ZQ Calibration Reset Timing Example .............................................................................................................. 64

7.4.24.5

ZQ External Resistor Value, Tolerance, and Capacitive Loading ...................................................................... 65

7.4.25

Power-Down................................................................................................................................................................ 65

7.4.25.1

Basic Power Down Entry and Exit Timing ......................................................................................................... 65

7.4.25.2

CKE Intensive Environment .............................................................................................................................. 66

7.4.25.3

Refresh to Refresh Timing with CKE Intensive Environment ............................................................................. 66

7.4.25.4

Read to Power-Down Entry............................................................................................................................... 67

7.4.25.5

Read with Auto Precharge to Power-Down Entry .............................................................................................. 67

7.4.25.6

Write to Power-Down Entry............................................................................................................................... 68

7.4.25.7

Write with Auto Precharge to Power-Down Entry .............................................................................................. 68

7.4.25.8

Refresh Command to Power-Down Entry.......................................................................................................... 69

7.4.25.9

Activate Command to Power-Down Entry ......................................................................................................... 69

7.4.25.10

Precharge/Precharge-All Command to Power-Down Entry ............................................................................... 69

7.4.25.11

Mode Register Read to Power-Down Entry....................................................................................................... 70

7.4.25.12

MRW Command to Power-Down Entry ............................................................................................................. 70

7.4.26

Deep Power-Down ...................................................................................................................................................... 70

7.4.26.1

Deep Power Down Entry and Exit Timing.......................................................................................................... 71

7.4.27

Input Clock Stop and Frequency Change .................................................................................................................... 71

7.4.28

No Operation Command.............................................................................................................................................. 72

7.5

Truth Tables................................................................................................................................................................. 72

7.5.1

Command Truth Table................................................................................................................................................. 73

7.5.2

CKE Truth Table.......................................................................................................................................................... 74

7.5.3

Current State Bank n - Command to Bank n Truth Table ............................................................................................. 75

7.5.4

Current State Bank n - Command to Bank m Truth Table ............................................................................................ 77

7.5.5

Data Mask Truth Table ................................................................................................................................................ 78

ELECTRICAL CHARACTERISTIC .............................................................................................................................. 79

8.1

Absolute Maximum DC Ratings ................................................................................................................................... 79

8.2

AC & DC Operating Conditions.................................................................................................................................... 79

8.2.1

Recommended DC Operating Conditions .................................................................................................................... 79

8.2.1.1

Recommended DC Operating Conditions ......................................................................................................... 79

8.2.2

Input Leakage Current................................................................................................................................................. 80

8.2.3

Operating Temperature Conditions.............................................................................................................................. 80

8.2.4

AC and DC Input Measurement Levels........................................................................................................................ 80

8.2.4.1

AC and DC Logic Input Levels for Single-Ended Signals................................................................................... 80

8.2.4.1.1

Single-Ended AC and DC Input Levels for CA and CS_n Inputs ....................................................................... 80

8.2.4.1.2

Single-Ended AC and DC Input Levels for CKE ................................................................................................ 81

8.2.4.1.3

Single-Ended AC and DC Input Levels for DQ and DM ..................................................................................... 81

8.2.4.2

Vref Tolerances ................................................................................................................................................ 81

8.2.4.2.1

VRef(DC) Tolerance and VRef AC-Noise Limits................................................................................................ 82

8.2.4.3

Input Signal....................................................................................................................................................... 83

8.2.4.3.1

LPDDR2-800/1066 Input Signal ........................................................................................................................ 83

8.2.4.4

AC and DC Logic Input Levels for Differential Signals....................................................................................... 84

8.2.4.4.1

Differential Signal Definition .............................................................................................................................. 84

8.2.4.4.2

Differential swing requirements for clock (CK_t - CK_c) and strobe (DQS_t - DQS_c) ...................................... 84

8.2.4.5

Single-Ended Requirements for Differential Signals .......................................................................................... 85

8.2.4.6

Differential Input Cross Point Voltage................................................................................................................ 86

8.2.4.7

Slew Rate Definitions for Single-Ended Input Signals ....................................................................................... 87

8.2.4.8

Slew Rate Definitions for Differential Input Signals............................................................................................ 87

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