W97AH6KB datasheet(13/127 Pages) WINBOND

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W97AH6KB / W97AH2KB

Publication Release Date: May 15, 2014

Revision: A01-001

- 13 -

FUNCTIONAL DESCRIPTION

LPDDR2-S4 devices use a double data rate architecture on the DQ pins to achieve high speed operation. The

double data rate architecture is essentially a 4n prefetch architecture with an interface designed to transfer two data

bits per DQ every clock cycle at the I/O pins. A single read or write access for the LPDDR2-S4 effectively consists of

a single 4n-bit-wide, one-clock-cycle data transfer at the internal SDRAM core and four corresponding n-bit-wide,

one-half-clock-cycle data transfers at the I/O pins.

Read and write accesses are burst oriented; accesses start at a selected location and continue for a programmed

number of locations in a programmed sequence.

Prior to normal operation, the LPDDR2 device must be initialized. The following section provides detailed information

covering device initialization, register definition, command description and device operation.

7.1

Simplified LPDDR2 State Diagram

LPDDR2-SDRAM state diagram provides a simplified illustration of allowed state transitions and the related

commands to control them. For a complete definition of the device behavior, the information provided by the state

diagram should be integrated with the truth tables and timing specification.

The truth tables provide complementary information to the state diagram, they clarify the device behavior and the

applied restrictions when considering the actual state of all the banks.

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