W97AH6KB datasheet(2/127 Pages) WINBOND

2 / 127 page

W97AH6KB / W97AH2KB

Publication Release Date: May 15, 2014

Revision: A01-001

- 2 -

7.4.3.3

Burst Read: RL = 5, BL = 4, tDQSCK > tCK...................................................................................................... 30

7.4.3.4

Burst Read: RL = 3, BL = 8, tDQSCK < tCK...................................................................................................... 31

7.4.3.5

LPDDR2: tDQSCKDL Timing ............................................................................................................................ 31

7.4.3.6

LPDDR2: tDQSCKDM Timing ........................................................................................................................... 32

7.4.3.7

LPDDR2: tDQSCKDS Timing............................................................................................................................ 32

7.4.3.8

Burst Read Followed by Burst Write: RL = 3, WL = 1, BL = 4 ............................................................................ 33

7.4.3.9

Seamless Burst Read: RL = 3, BL= 4, tCCD = 2 ............................................................................................... 33

7.4.4

Reads Interrupted by a Read....................................................................................................................................... 34

7.4.4.1

Read Burst Interrupt Example: RL = 3, BL= 8, tCCD = 2 ................................................................................... 34

7.4.5

Burst Write Operation .................................................................................................................................................. 34

7.4.5.1

Data Input (Write) Timing .................................................................................................................................. 35

7.4.5.2

Burst Write: WL = 1, BL= 4 ............................................................................................................................... 35

7.4.5.3

Burst Wirte Followed by Burst Read: RL = 3, WL= 1, BL= 4.............................................................................. 36

7.4.5.4

Seamless Burst Write: WL= 1, BL = 4, tCCD = 2............................................................................................... 36

7.4.6

Writes Interrupted by a Write ....................................................................................................................................... 37

7.4.6.1

Write Burst Interrupt Timing: WL = 1, BL = 8, tCCD = 2 .................................................................................... 37

7.4.7

Burst Terminate........................................................................................................................................................... 37

7.4.7.1

Burst Write Truncated by BST: WL = 1, BL = 16 ............................................................................................... 38

7.4.7.2

Burst Read Truncated by BST: RL = 3, BL = 16................................................................................................ 38

7.4.8

Write Data Mask.......................................................................................................................................................... 39

7.4.8.1

Write Data Mask Timing.................................................................................................................................... 39

7.4.9

Precharge Operation ................................................................................................................................................... 40

7.4.9.1

Bank Selection for Precharge by Address Bits .................................................................................................. 40

7.4.10

Burst Read Operation Followed by Precharge ............................................................................................................. 40

7.4.10.1

Burst Read Followed by Precharge: RL = 3, BL = 8, RU(tRTP(min)/tCK) = 2 .................................................... 41

7.4.10.2

Burst Read Followed by Precharge: RL = 3, BL = 4, RU(tRTP(min)/tCK) = 3 .................................................... 41

7.4.11

Burst Write Followed by Precharge ............................................................................................................................. 42

7.4.11.1

Burst Write Follwed by Precharge: WL = 1, BL = 4............................................................................................ 42

7.4.12

Auto Precharge Operation ........................................................................................................................................... 43

7.4.13

Burst Read with Auto-Precharge ................................................................................................................................. 43

7.4.13.1

Burst Read with Auto-Precharge: RL = 3, BL = 4, RU(tRTP(min)/tCK) = 2 ........................................................ 43

7.4.14

Burst Write with Auto-Precharge.................................................................................................................................. 44

7.4.14.1

Burst Write with Auto-Precharge: WL = 1, BL = 4.............................................................................................. 44

7.4.14.2

Precharge & Auto Precharge Clarification ......................................................................................................... 45

7.4.15

Refresh Command ...................................................................................................................................................... 46

7.4.15.1

Command Scheduling Separations Related to Refresh..................................................................................... 47

7.4.16

LPDDR2 SDRAM Refresh Requirements .................................................................................................................... 47

7.4.16.1

Definition of tSRF.............................................................................................................................................. 48

7.4.16.2

Regular, Distributed Refresh Pattern................................................................................................................. 50

7.4.16.3

Allowable Transition from Repetitive Burst Refresh........................................................................................... 50

7.4.16.4

NOT-Allowable Transition from Repetitive Burst Refresh .................................................................................. 51

7.4.16.5

Recommended Self-Refresh Entry and Exit ...................................................................................................... 51

7.4.16.6

All Bank Refresh Operation............................................................................................................................... 52

7.4.16.7

Per Bank Refresh Operation ............................................................................................................................. 52

7.4.17

Self Refresh Operation ................................................................................................................................................ 53

7.4.18

Partial Array Self-Refresh: Bank Masking.................................................................................................................... 54

7.4.19

Partial Array Self-Refresh: Segment Masking .............................................................................................................. 54

7.4.20

Mode Register Read Command .................................................................................................................................. 55

7.4.20.1

Mode Register Read Timing Example: RL = 3, tMRR = 2.................................................................................. 56

7.4.20.2

Read to MRR Timing Example: RL = 3, tMRR = 2 ............................................................................................ 57

7.4.20.3

Burst Write Followed by MRR: RL = 3, WL = 1, BL = 4 ..................................................................................... 57

7.4.21

Temperature Sensor.................................................................................................................................................... 58

7.4.21.1

Temperature Sensor Timing ............................................................................................................................. 59

7.4.21.2

DQ Calibration .................................................................................................................................................. 59

7.4.21.3

MR32 and MR40 DQ Calibration Timing Example: RL = 3, tMRR = 2 ............................................................... 60

7.4.22

Mode Register Write Command................................................................................................................................... 61

W97AH6KB датащи(PDF) 2 Page - Winbond

W97AH6KB датащи(HTML) 2 Page - Winbond

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL