PUSB3FR4

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© NXP Semiconductors N.V. 2015. All rights reserved.

Product data sheet

Rev. 1 — 26 January 2015

7 of 15

NXP Semiconductors

PUSB3FR4

ESD protection for ultra high-speed interfaces

The device uses an advanced clamping structure showing a negative dynamic resistance.

This snap-back behavior strongly reduces the clamping voltage to the system behind the

ESD protection during an ESD event. Do not connect unlimited DC current sources to the

data lines to avoid keeping the ESD protection device in snap-back state after exceeding

breakdown voltage (due to an ESD pulse for instance).

Fig 9.

Dynamic resistance with positive clamping;

typical values

Fig 10. Dynamic resistance with negative clamping;

typical values

Fig 11. Dynamic resistance with positive clamping;

typical values

Fig 12. Dynamic resistance with negative clamping;

typical values

030

20

10

aaa-016322

10

20

30

(A)

0

-30

0

-10

-20

aaa-016323

-20

-10

0

(A)

-30

020

15

510

aaa-016324

10

5

15

20

(A)

0

-12

0

-4

-8

aaa-016325

-8

-4

0

(A)

-12