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UPD78P324LP датащи(PDF) 36 Page - NEC |
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UPD78P324LP датащи(HTML) 36 Page - NEC |
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36 / 80 page ![]() µPD78P324, 78P324(A) 36 (2) µPD78P324(A) Electrical Specifications (5/9) AC Characteristics (TA = –40 to +85 °C, VDD = +5 V ±10%, VSS = 0 V, CL = 100pF) Non-serial Read/Write Operation (when connecting general-purpose memory) Parameter Symbol Condition MIN. MAX. Unit System clock cycle time tCYK 125 250 ns Address setup time (vs. ASTB ↓)tSAST 32 ns Address hold time (vs. ASTB ↓)tHSTA 32 ns Address → RD ↓ delay time tDAR 85 ns RD ↓ → address float time tFRA 10 ns Address → data input time tDAID 222 ns RD ↓ → data input time tDRID 112 ns ASTB ↓ → RD ↓ delay time tDSTR 42 ns Data hold time (vs. RD ↑)tHRID 0ns RD ↑ → address active time tDRA 50 ns RD low-level width tWRL 147 ns ASTB high-level width tWSTH 37 ns Address → WR ↓ delay time tDAW 85 ns ASTB ↓ → data output time tDSTOD 102 ns WR ↓ → data output time tDWOD 40 ns ASTB ↓ → WR ↓ delay time tDSTW 42 ns Data setup time (vs. WR ↑)tSODW 147 ns Data hold time (vs. WR ↑)tHWOD 32 ns WR ↑ → ASTB ↑ delay time tDWST 42 ns WR low-level width tWWL 147 ns |
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