UPD78P324LP datasheet(29/80 Pages) NEC

номер детали	UPD78P324LP

подробное описание детали	16-/8-Bit Single-Chip Microcomputers

PDF	80 Pages

Scroll/Zoom	100%

производитель	NEC [NEC]

домашняя страница	http://www.nec.com/

Logo

29 / 80 page

µPD78P324, 78P324(A)

(1)

µPD78P324 Electrical Specifications (7/9)

Serial Operation (TA = –10 to +70

°C, VDD = +5 V ±10 %, VSS = 0 V)

Parameter

Symbol

Condition

MIN.

MAX.

Unit

SCK output

Internal divide-by-eight

µs

Serial clock cycle time

tCYSK

SCK input

External clock

µs

SCK output

Internal divide-by-eight

420

Serial clock low-level width

tWSKL

SCK input

External clock

420

SCK output

Internal divide-by-eight

420

Serial clock high-level width

tWSKH

SCK input

External clock

420

SI setup time (vs. SCK

↑)tSRXSK

SI hold time (vs. SCK

↑)tHSKRX

SCK

↓ → SO delay time

tDSKTX

R = 1 k

Ω , C = 100pF

210

tCYK-dependent Serial Operation

Symbol

Condition

Calculation Formula

MIN./MAX.

Unit

SCK output

Internal divide-by-eight

MIN.

tCYSK

SCK input

External clock

MIN.

SCK output

Internal divide-by-eight

4T–80

MIN.

tWSKL

SCK input

External clock

4T–80

MIN.

SCK output

Internal divide-by-eight

4T–80

MIN.

tWSKH

SCK input

External clock

4T–80

MIN.

Remarks

1. T = tCYK = 1/fCLK (fCLK refers to the internal system clock frequency)

2. Among the parameters for serial operation, only those listed in this table are dependent on tCYK.

UPD78P324LP датащи(PDF) 29 Page - NEC

UPD78P324LP датащи(HTML) 29 Page - NEC

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

датащи скачать

ссылки URL