UPD78C18 datasheet(71/110 Pages) NEC

номер детали	UPD78C18

подробное описание детали	8-BIT SINGLE-CHIP MICROCONTROLLER WITH A/D CONVERTER

PDF	110 Pages

Scroll/Zoom	100%

производитель	NEC [NEC]

домашняя страница	http://www.nec.com/

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71 / 110 page

µPD78C17,78C18

Fig. 4-7 Hardware STOP Mode Release Timing

Fig. 4-8 Hardware STOP Mode Release Timing

In the case of a hardware STOP mode release, as with a release of the software STOP mode by means of the

RESET signal, it is possible to differentiate between a power-on start and a start due to release of the hardware

STOP mode by testing the SB flag using a skip instruction.

4.7

LOW SUPPLY VOLTAGE DATA RETENTION MODE

The low supply voltage data retention mode can be set by decreasing the VDD supply voltage to 2.5 V after

setting the software/hardware STOP mode. RAM contents can be retained with lower power consumption than

in the software/hardware STOP mode.

Caution

The software/hardware STOP mode should not be released while in the low supply voltage data

retention mode. VDD must be raised to the normal operating voltage before the release is per-

formed.

CPU

Operation

Instruction

Execution

Address 0 Instruction

Execution

STOP

OSC

Wait

RESET

CPU

Operation

Instruction

Execution

Address 0 Instruction

Execution

STOP

OSC

Wait

RESET

UPD78C18 датащи(PDF) 71 Page - NEC