UPD78C18 datasheet(39/110 Pages) NEC

39 / 110 page

µPD78C17,78C18

(1)

Timer/event counter mode register (ETMM)

This is an 8-bit register which controls the timer/event counter (see Fig. 2-21).

The timer/event counter mode register bits 0 and 1 (ET0, ET1) control the timer event counter upcounter

(ECNT) input clock, bits 2 and 3 (EM0, EM1) control the ECNT clear mode, bits 4 and 5 (CO00, CO01)

control output timing when the output latch contents are output to the counter output0 (CO0). Bits 6 and 7

(CO10, CO11) control CO1 output timing.

The internal clock (

φ12) divides the oscillation frequency by 12.

After RESET input or in the hardware STOP mode, the timer/event counter mode register is reset to 00H.

Fig. 2-21 Timer/Event Counter Mode Register Format

76543210

CO11

CO10

CO01

CO00

EM 1

EM 0

ET 1

ET 0

Internal clock (

φ12)

φ12 while CI input is in the high level

CI input

CI input while TO is in the high level

ECNT Input Clock

ETMM

ECNT Clear Mode

Stop after clear

Free running

Clear a full count at a time

Clear by matching ECNT and ETM1

Clear at the fall of CI input (ET1 = 0)

Clear the fall of TO

(ET1 = 1)

CO0 Output Timing

ECNT and ETM0 match

Setting prohibited

ECNT and ETM0 match, or

CI input fall

ECNT and ETM0 match, or

ECNT and ETM1 match

CO1 Output Timing

ECNT and ETM1 match

Setting prohibited

ECNT and ETM1 match, or

CI input fall

ECNT and ETM0 match, or

ECNT and ETM1 match

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