LTC1418AIN datasheet(7/28 Pages) LINER

7 / 28 page

LTC1418

PIN FUNCTIONS

AIN

+ (Pin 1): Positive Analog Input.

AIN

– (Pin 2): Negative Analog Input.

VREF (Pin 3): 2.50V Reference Output. Bypass to AGND

with 1

µF.

REFCOMP (Pin 4): 4.096V Reference Bypass Pin.

Bypass to AGND with 10

µF tantalum in parallel with 0.1µF

ceramic.

AGND (Pin 5): Analog Ground.

D13 to D6 (Pins 6 to 13): Three-State Data Outputs

(Parallel). D13 is the most significant bit.

DGND (Pin 14): Digital Ground for Internal Logic. Tie to

AGND.

D5 (Pin 15): Three-State Data Output (Parallel).

D4 (EXTCLKIN) (Pin 16): Three-State Data Output

(Parallel). Conversion clock input (serial) when Pin 20

(EXT/INT) is tied high.

D3 (SCLK) (Pin 17): Three-State Data Output (Parallel).

Data clock input (serial).

D2 (CLKOUT) (Pin 18): Three-State Data Output (Parallel).

Conversion clock output (serial).

D1 (DOUT) (Pin 19): Three-State Data Output (Parallel).

Serial data output (serial).

D0 (EXT/INT) (Pin 20): Three-State Data Output (Parallel).

Conversion clock selector (serial). An input low enables

the internal conversion clock. An input high indicates an

external conversion clock will be assigned to Pin 16

(EXTCLKIN).

SER/PAR (Pin 21): Data Output Mode.

SHDN (Pin 22): Power Shutdown Input. Low selects

shutdown. Shutdown mode selected by CS. CS = 0 for nap

mode and CS = 1 for sleep mode.

RD (Pin 23): Read Input. This enables the output drivers

when CS is low.

CONVST (Pin 24): Conversion Start Signal. This active low

signal starts a conversion on its falling edge.

CS (Pin 25): Chip Select. This input must be low for the

ADC to recognize the CONVST and RD inputs. CS also sets

the shutdown mode when SHDN goes low. CS and SHDN

low select the quick wake-up nap mode. CS high and

SHDN low select sleep mode.

BUSY (Pin 26): The BUSY Output Shows the Converter

Status. It is low when a conversion is in progress.

VSS (Pin 27): Negative Supply, –5V for Bipolar Operation.

Bypass to AGND with 10

µF tantalum in parallel with 0.1µF

ceramic. Analog ground for unipolar operation.

VDD (Pin 28): 5V Positive Supply. Bypass to AGND with

µF tantalum in parallel with 0.1µF ceramic.

TEST CIRCUITS

DBN

DGND

A) HI-Z TO VOH AND VOL TO VOH

DBN

B) HI-Z TO VOL AND VOH TO VOL

DGND

1418 TC01

Load Circuits for Access Timing

Load Circuits for Output Float Delay

30pF

DBN

A) VOH TO HI-Z

30pF

DBN

B) VOL TO HI-Z

1418 TC02

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