LTC1418AIN datasheet(25/28 Pages) LINER

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LTC1418

APPLICATIONS INFORMATION

also allows operation when the SCLK frequency is very low

(less than 30kHz). To select the internal conversion clock

tie EXT/INT low. The external SCLK is applied to SCLK. RD

can be used to gate the external SCLK, such that data will

clock only after RD goes low and to three-state DOUT after

data transfer. If more than 16 SCLKs are provided, more

zeros will be filled in after the data word indefinitely.

LTC1418

BUSY

CONVST

EXTCLKIN

SCLK

EXT/INT

DOUT

1418 F25a

µP OR DSP

CLKOUT

INT

SCK

MISO

123456789 10 11 12 13 14 15 16

CS = 0, EXT/INT = 5

CONVST

EXTCLKIN

t13

tdEXTCLKIN

HOLD

SAMPLE

t11

BUSY

SCLK

123456789 10 11 12 13 14 15 16

12 11 10 987654321

FILL

ZEROS

D13

Hi-Z

DATA N

Hi-Z

(SAMPLE N)

DOUT

tCONV

t10

1418 F25b

D11

D12

CAPTURE ON

RISING CLOCK

D13

t15

t14

SCLK

VIL

VOH

VOL

DOUT

CAPTURE ON

FALLING CLOCK

tLSCLK

tHSCLK

Figure 25. External Conversion Clock Selected. Data Transferred After Conversion

Using an External SCLK. BUSY

↑ Indicates End of Conversion

Using External Conversion Clock and External Data

Clock. In Figure 25, data is also output after each conver-

sion is completed and before the next conversion is

started. An external clock is used for the conversion clock

and either another or the same external clock is used for

the SCLK. This mode is identical to Figure 24 except that

an external clock is used for the conversion. This mode

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