LTC1404CS8 datasheet(4/24 Pages) LINER

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LTC1404

(Note 5)

DIGITAL I PUTS AND OUTPUTS

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

IOZ

Hi-Z Output Leakage DOUT

VOUT = 0V to VCC

±10

µA

COZ

Hi-Z Output Capacitance DOUT

ISOURCE

Output Source Current

VOUT = 0V

– 10

ISINK

Output Sink Current

VOUT = VCC

TI I G CHARACTERISTICS (Note 5, see Figures 12, 13, 14)

The q denotes specifications which apply over the full operating

temperature range; all other limits and typicals apply to TA = 25°C.

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: All voltage values are with respect to GND.

Note 3: When these pin voltages are taken below VSS (ground for unipolar

mode) or above VCC, they will be clamped by internal diodes. This product

can handle input currents greater than 60mA without latch-up if the pin is

driven below VSS (ground for unipolar mode) or above VCC.

Note 4: When these pin voltages are taken below VSS (ground for unipolar

mode), they will be clamped by internal diodes. This product can handle

input currents greater than 60mA without latch-up if the pin is driven

below VSS (ground for unipolar mode). These pins are not clamped to VCC.

Note 5: VCC = 5V, fSAMPLE = 600kHz, tr = tf = 5ns unless otherwise

specified.

Note 6: Guaranteed by design, not subject to test.

Note 7: Linearity, offset and full-scale specifications apply for unipolar and

bipolar modes.

Note 8: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 9: Bipolar offset is the offset voltage measured from – 0.5LSB when

the output code flickers between 0000 0000 0000 and 1111 1111 1111.

Note 10: The rising edge of CONV starts a conversion. If CONV returns

low at a bit decision point during the conversion, it can create small errors.

For best performance, ensure that CONV returns low either within 100ns

after the conversion starts (i.e., before the first bit decision) or after the 14

clock cycles. (Figure 13 Timing Diagram).

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

fSAMPLE(MAX)

Maximum Sampling Frequency

600

kHz

tCONV

Conversion Time

fCLK = 9.6MHz

1.36

µs

tACQ

Acquisition Time (Unipolar Mode)

200

(Bipolar Mode VSS = – 5V)

160

fCLK

CLK Frequency

0.1

9.6

MHz

tCLK

CLK Pulse Width

(Note 6)

tWK(NAP)

Time to Wake Up from Nap Mode

350

CLK Pulse Width to Return to Active Mode

CONV

↑ to CLK↑ Setup Time

CONV

↑ After Leading CLK↑

0ns

CONV Pulse Width

(Note 10)

Time from CLK

↑ to Sample Mode

Aperture Delay of Sample-and-Hold

Jitter < 50ps

Minimum Delay Between Conversion (Unipolar Mode)

(Note 6)

220

310

(Bipolar Mode VSS = – 5V)

180

300

Delay Time, CLK

↑ to DOUT Valid

CLOAD = 20pF

Delay Time, CLK

↑ to DOUT Hi-Z

CLOAD = 20pF

t10

Time from Previous Data Remains Valid After CLK

↑

CLOAD = 20pF

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