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LTC1404CS8 датащи(PDF) 15 Page - Linear Technology |
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LTC1404CS8 датащи(HTML) 15 Page - Linear Technology |
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15 / 24 page ![]() 15 LTC1404 APPLICATIONS INFORMATION BOARD LAYOUT AND BYPASSING To obtain the best performance from the LTC1404, a printed circuit board is required. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital traces alongside an analog signal trace or underneath the ADC. The analog input should be screened by GND. High quality 10 µF surface mount AVX capacitor with a 0.1 µF ceramic should be used at the VCC, VSS and VREF pins. For better results, another 10 µFAVXcapacitorcanbe added to the VCC pin. At 600ksps, the CLK frequency can be as high as 9.6MHz. A poor quality capacitor can lose more than 80% of its capacitance at this frequency range. Therefore, it is important to consult the manufacturer’s data sheet before the capacitor is used. For the LTC1404, at 600ksps, every bit decision must be determined within 104ns (9.6MHz). During this short time interval, the supply disturbance due to a CLK transition needs to settle. The ADC must update its DAC, make a comparator deci- sion based on sub-mV overdrive, latch the new DAC information and output the serial data. This ADC provides one power supply, VCC, which is connected to both the internal analog and digital circuitry. Any ringing due to poor supply or reference bypassing, inductive trace runs, CLK and CONV over- or undershoot, or unnecessary DOUT loading can cause ADC errors. Therefore, the bypass capacitors must be located as close to the pins as possible. The traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. In unipolar mode operation, VSS must be con- nected to the GND pin directly. Input signal leads to AIN and signal return leads from GND (Pin 4) should be kept as short as possible to minimize noise coupling. In applications where this is not possible, a shielded cable between the analog input signal and the ADC is recommended. Also, any potential difference in grounds between the analog signal and the ADC appears as an error voltage in series with the analog input signal. Attention should be paid to reducing the ground circuit impedance as much as possible. Figure 11 shows the recommended system ground con- nections. All analog circuitry grounds should be termi- nated at the LTC1404 GND pin. The ground return from the LTC1404 Pin 4 to the power supply should be low imped- ance for noise free operation. Digital circuitry grounds must be connected to the digital supply common. As an alternative, instead of a direct short between the digital and analog circuitry, a 10 Ω or a ferrite bead jumper helps reduce the digital noise. ANALOG SUPPLY –5V GND 5V + + LTC1404 VSS VCC GND DIGITAL SUPPLY GND 5V + DIGITAL CIRCUITRY VCC GND 1404 F11 Figure 11. Power Supply Connection In applications where the ADC data outputs and control signals are connected to a continuously active micropro- cessor bus, it is possible to get errors in the conversion results. These errors are due to feedthrough from the microprocessor to the successive approximation com- parator. The problem can be eliminated by forcing the microprocessor into a Wait state during conversion or by using three-state buffers to isolate the ADC data bus. Power-Down Mode Upon power-up, the LTC1404 is initialized to the active state and is ready for conversion. However, the chip can be easily placed into Nap or Sleep mode by exercising the right combination of CLK and CONV signals. In Nap mode, all power is off except for the internal reference, which is still active and provides 2.43V output voltage to the other circuitry. In this mode, the ADC draws only 7.5mW of power instead of 75mW (for minimum power, the logic |
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