21

Specifications ispGDX80VA

Boundary Scan

The ispGDXVA devices provide IEEE1149.1a test capa-

bility and ISP programming through a standard Boundary

Scan Test Access Port (TAP) interface.

The boundary scan circuitry on the ispGDXVA Family

operates independently of the programmed pattern. This

allows customers using boundary scan test to have full

test capability with only a single BSDL file.

The ispGDXVA devices are identified by the 32-bit JTAG

IDCODE register. The device ID assignments are listed

in Table 4.

Table 3. I/O Shift Register Order

Figure 10. Boundary Scan Register Circuit for I/O Pins

Normal

Function

OE

EXTEST

Update DR

SCANOUT

(to next cell)

Clock DR

SCANIN

(from previous

cell

Shift DR

Normal

Function

TOE

DQ

DQ

DQ

DQ

DQ

I/O Pin

Reset

BSCAN

Registers

BSCAN

Latches

HIGHZ

0

1

0

1

PROG_MODE

EXTEST

I/O Shift Reg Order/ispGDXVA

ispGDX80VA

TDI, TOE,

RESET, Y1, Y0, I/O B10 .. B19, I/O C0 .. C19, I/O D0 .. D9, I/O B9 .. B0, I/O A19.. A0,

I/O D19 .. D10, TDO

I/O SHIFT REGISTER ORDER

DEVICE

Table 4. ispGDX80VA Device ID Codes

ID Code/GDX80VA

ispGDX80VA

0001, 0000, 0011, 0101, 0000, 0000, 0100, 0011

32-BIT BOUNDARY SCAN ID CODE

DEVICE