80VA datasheet(20/27 Pages) LATTICE

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Specifications ispGDX80VA

Figure 9. ispJTAG Device Programming Interface

In-System Programmability

All necessary programming of the ispGDXVA is done via

four TTL level logic interface signals. These four signals

are fed into the on-chip programming circuitry where a

state machine controls the programming.

On-chip programming can be accomplished using an

IEEE 1149.1 boundary scan protocol. The IEEE 1149.1-

compliant interface signals are Test Data In (TDI), Test

Data Out (TDO), Test Clock (TCK) and Test Mode Select

(TMS) control. The EPEN pin is also used to enable or

disable the JTAG port.

The embedded controller port enable pin (EPEN) is used

to enable the JTAG tap controller and in that regard has

similar functionality to a TRST pin. When the pin is driven

high, the JTAG TAP controller is enabled. This is also true

when the pin is left unconnected, in which case the pin is

pulled high by the permanent internal pullup. This allows

ISP programming and BSCAN testing to take place as

specified by the Instruction Table.

When the pin is driven low, the JTAG TAP controller is

driven to a reset state asynchronously. It stays there

while the pin is held low. After pulling the pin high the

JTAG controller becomes active. The intent of this fea-

ture is to allow the JTAG interface to be directly controlled

by the data bus of an embedded controller (hence the

name Embedded Port Enable). The EPEN signal is used

as a “device select” to prevent spurious programming

and/or testing from occuring due to random bit patterns

on the data bus. Figure 9 illustrates the block diagram for

the ispJTAG interface.

ispGDX

80VA

Device

TDO

TDI

TMS

TCK

EPEN

ispJTAG

Programming

Interface

ispLSI

Device

ispMACH

Device

ispGDX

80VA

Device

ispGDX

80VA

Device

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