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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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80VA датащи(PDF) 14 Page - Lattice Semiconductor |
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80VA датащи(HTML) 14 Page - Lattice Semiconductor |
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14 / 27 page  14 Specifications ispGDX80VA -3 -5 PARAMETER # DESCRIPTION1 MIN. MAX. MIN. MAX. UNITS Inputs tio 32 Input Buffer Delay — 0.4 — 0.9 ns GRP tgrp 33 GRP Delay — 1.1 — 1.1 ns MUX tmuxd 34 I/O Cell MUX A/B/C/D Data Delay — 1.0 — 1.5 ns tmuxexp 35 I/O Cell MUX A/B/C/D Expander Delay — 1.5 — 2.0 ns tmuxs 36 I/O Cell Data Select — 1.0 — 1.5 ns tmuxsio 37 I/O Cell Data Select (I/O Clock) — 1.5 — 3.0 ns tmuxsg 38 I/O Cell Data Select (Yx Clock) — 1.5 — 2.0 ns tmuxselexp 39 I/O Cell MUX Data Select Expander Delay — 1.5 — 2.0 ns Register tiolat 40 I/O Latch Delay — 1.0 — 1.0 ns tiosu 41 I/O Register Setup Time Before Clock — 0.8 — 2.0 ns tioh 42 I/O Register Hold Time After Clock — 1.7 — 1.5 ns tioco 43 I/O Register Clock to Output Delay — 1.2 — 0.5 ns tior 44 I/O Reset to Output Delay — 1.0 — 1.5 ns tcesu 45 I/O Clock Enable Setup Time Before Clock — 2.3 — 2.0 ns tceh 46 I/O Clock Enable Hold Time After Clock — 0.2 — 0.5 ns Data Path tfdbk 47 I/O Register Feedback Delay — 0.6 — 0.9 ns tiobp 48 I/O Register Bypass Delay — 0.0 — 0.0 ns tioob 49 I/O Register Output Buffer Delay — 0.0 — 0.0 ns tmuxcg 50 I/O Register A/B/C/D Data Input MUX Delay (Yx Clock) — 1.5 — 2.0 ns tmuxcio 51 I/O Register A/B/C/D Data Input MUX Delay (I/O Clock) — 1.5 — 3.0 ns tiodg 52 I/O Register I/O MUX Delay (Yx Clock) — 3.5 — 4.0 ns tiodio 53 I/O Register I/O MUX Delay (I/O Clock) — 3.5 — 5.0 ns Outputs tob 54 Output Buffer Delay — 1.0 — 1.5 ns tobs 55 Output Buffer Delay (Slow Slew Option) — 4.5 — 6.5 ns toeen 56 I/O Cell OE to Output Enable — 3.5 — 4.0 ns toedis 57 I/O Cell OE to Output Disable — 3.5 — 4.0 ns tgoe 58 GRP Output Enable and Disable Delay — 0.0 — 0.0 ns ttoe 59 Test OE Enable and Disable Delay — 2.5 — 2.0 ns Clocks tioclk 60 I/O Clock Delay — 0.3 — 2.0 ns tgclk 61 Global Clock Delay — 1.3 — 2.0 ns tgclkeng 62 Global Clock Enable (Yx Clock) — 1.5 — 2.5 ns tgclkenio 63 Global Clock Enable (I/O Clock) — 1.0 — 3.5 ns tioclkeng 64 I/O Clock Enable (Yx Clock) — 0.5 — 2.5 ns Global Reset tgr 65 Global Reset to I/O Register Latch — 6.0 — 11.0 ns Internal Timing Parameters1 Over Recommended Operating Conditions 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to the Timing Model in this data sheet for further details. |
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