AN4228 datasheet(22/90 Pages) STMICROELECTRONICS

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Peripheral migration

AN4228

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DocID024110 Rev 5

3.4.3

Peripheral clock configuration

Some peripherals have a dedicated clock source independent from the system clock, and

used to generate the clock required for them to operate:



ADC

In STM32F30xx devices, the ADC features two possible clock sources:

–

The ADC clock can be derived from the PLL output. It can reach 72 MHz and can

be divided by the following prescalers values: 1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128,

or 256. It is asynchronous to the AHB clock

–

The ADC clock can also be derived from the AHB clock of the ADC bus interface,

divided by a programmable factor (1, 2 or 4). When the programmable factor is 1,

the AHB prescaler must be equal to '1'.



SDADC

STM32F37xx SDADC clock source is derived from the system clock divided by a wide

range of prescalers, ranging from 2 to 48.



RTC

In STM32F3 series, the RTC features three possible clock sources:

–

The first one is based on the HSE Clock; a prescaler divides its frequency by 32

before going to the RTC

–

The second one is the LSE oscillator

–

The third clock source is the LSI RC with a value of 40 kHz.



TIMx

The timers clock frequencies are automatically defined by hardware. There are two

cases:

–

If the APB prescaler equals 1, the timer clock frequencies are set to the same

frequency as that of the APB domain

–

Otherwise, they are set to twice (×2) the frequency of the APB domain.

PLL clock source

A clock issued from the PLL (PLLCLKx2) can be selected for TIMx (x = 1, 8 on the

STM32F303xB/C, x = 1 on the STM32F303x6/8, x = 1, 15, 16, 17 on the

STM32F302/301x6/8), x = 1,2,3,4,8,15,16,17,20 in the STM32F303xD/E.

This configuration allows to feed TIMx with a frequency up to 144 MHz when the

system clock source is the PLL. In this configuration:

–

On the STM32F303/302xB/C, AHB and APB2 prescalers are set to 1 i.e. AHB and

APB2 clocks are not divided with respect to the system clock

–

On the STM32F303/302/301x6/8 and STM32F302/303xD/E, AHB or APB2

subsystem clocks are not divided by more than 2 cumulatively with respect to the

system clock.



I2S

In STM32F30xx devices, the I2S features 2 possible clock sources:

–

The first one is the System clock

–

The second one comes from the external clock provided on I2S_CKIN pin.

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