AN4228 datasheet(20/90 Pages) STMICROELECTRONICS

20 / 90 page

Peripheral migration

AN4228

20/90

DocID024110 Rev 5

Table 10. Example of migrating system clock configuration code from STM32F100 to STM32F3xx

STM32F100 Value Line running at 24 MHz

(PLL as clock source) with 0 wait states

STM32F3xx running at 48 MHz

(PLL as clock source) with 1 wait state

/* Enable HSE -------------------------*/

RCC->CR |= ((uint32_t)RCC_CR_HSEON);

/* Wait till HSE is ready */

while((RCC->CR & RCC_CR_HSERDY) == 0)

{

}

/* Flash configuration --------------*/

/* Prefetch ON, Flash 0 wait state */

FLASH->ACR |= FLASH_ACR_PRFTBE |

FLASH_ACR_LATENCY_0;

/*AHB and APB prescaler configuration*/

/* HCLK = SYSCLK */

RCC->CFGR |=

(uint32_t)RCC_CFGR_HPRE_DIV1;

/* PCLK2 = HCLK */

RCC->CFGR |=

(uint32_t)RCC_CFGR_PPRE2_DIV1;

/* PCLK1 = HCLK */

RCC->CFGR |=

(uint32_t)RCC_CFGR_PPRE1_DIV1;

/* PLL configuration = (HSE / 2) * 6 =

24 MHz */

RCC->CFGR |=

(uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 |

RCC_CFGR_PLLXTPRE_PREDIV1_Div2 |

RCC_CFGR_PLLMULL6);

/* Enable PLL */

RCC->CR |= RCC_CR_PLLON;

/* Wait till PLL is ready */

while((RCC->CR & RCC_CR_PLLRDY) == 0)

{

}

/* Select PLL as system clock source --*/

RCC->CFGR &=

(uint32_t)((uint32_t)~(RCC_CFGR_SW));

RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;

/* Wait till PLL is used as system clock

source */

while ((RCC->CFGR &

(uint32_t)RCC_CFGR_SWS) !=

(uint32_t)0x08)

{

}

/* Enable HSE -------------------------*/

RCC->CR |= ((uint32_t)RCC_CR_HSEON);

/* Wait till HSE is ready */

while((RCC->CR & RCC_CR_HSERDY) == 0)

{

}

/* Flash configuration ----------------*/

/* Prefetch ON, Flash 1 wait state */

FLASH->ACR |= FLASH_ACR_PRFTBE |

FLASH_ACR_LATENCY;

/* AHB and APB prescaler configuration-*/

/* HCLK = SYSCLK */

RCC->CFGR |=

(uint32_t)RCC_CFGR_HPRE_DIV1;

/* PCLK = HCLK */

RCC->CFGR |=

(uint32_t)RCC_CFGR_PPRE_DIV1;

/* PLL configuration = HSE * 6 = 48 MHz -*/

RCC->CFGR |=

(uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 |

RCC_CFGR_PLLXTPRE_PREDIV1 |

RCC_CFGR_PLLMULL6);

/* Enable PLL */

RCC->CR |= RCC_CR_PLLON;

/* Wait till PLL is ready */

while((RCC->CR & RCC_CR_PLLRDY) == 0)

{

}

/* Select PLL as system clock source ---*/

RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;

/* Wait till PLL is used as system clock

source */

while ((RCC->CFGR &

(uint32_t)RCC_CFGR_SWS) !=

(uint32_t)RCC_CFGR_SWS_PLL)

{

}

AN4228 датащи(PDF) 20 Page - STMicroelectronics

AN4228 датащи(HTML) 20 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

датащи скачать

ссылки URL