AN4228 datasheet(18/90 Pages) STMICROELECTRONICS

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Peripheral migration

AN4228

18/90

DocID024110 Rev 5

In addition to the differences described in the table above, the following additional

adaptation steps may be needed for the migration:



System clock configuration



Peripheral access configuration



Peripheral clock configuration

3.4.1

System clock configuration

When moving from STM32F1 series to STM32F3 series, only a few settings need to be

updated in the system clock configuration code; mainly the Flash settings (configure the

right wait states for the system frequency, prefetch enable/disable) or/and the PLL

parameters configuration:



If HSE or HSI is used directly as the system clock source, only the Flash parameters

should be modified.



If PLL (clocked by HSE or HSI) is used as the system clock source, the Flash

parameters and PLL configuration need to be updated.

Table 10 below provides an example of how to port a system clock configuration from

STM32F1 to STM32F3 series:



STM32F100xx value line running at maximum performance: system clock at 24 MHz

(PLL, clocked by the HSE (8 MHz), used as the system clock source), Flash with 0 wait

states and Flash prefetch queue enabled.



STM32F3 series running at maximum performance: system clock at 72 MHz (PLL,

clocked by the HSE (8 MHz), used as the system clock source), Flash with 2 wait

states and Flash prefetch enabled.

Note:

In STM32F30xxD/E, we can reach the maximum system clock 72 MHz when PLL is system

clock source and PLL clock source is the HSI. In STM32F1 and other STM32F3 series

devices, when PLL clock source is the HSI, the maximum system clock value is 64 MHz.

As shown in Table 10, only the Flash settings and PLL parameters (code in Bold Italic)

need to be rewritten to run on STM32F3 series. However, HSE, AHB prescaler and the

MCO clock

source

MCO pin (PA8):

– Connectivity line: HSI, HSE,

PLLCLK/2, SYSCLK, PLL2, PLL3

or XT1

– Other product lines: HSI, HSE,

PLLCLK/2 or SYSCLK

STM32F302/303xB/C and STM32F37x:

SYSCLK, HSI, HSE, PLLCLK/2, LSE, LSI.

STM32F302/301/303x6/x8: SYSCLK, HSI,

HSE, PLLCLK/2 or PLLCLK, LSE, LSI; with

the possibility to reduce MCO frequency by

a configurable divider.

Internal

oscillator

measurement /

calibration

LSI connected to TIM5 CH4 IC: can

measure LSI with respect to HSI/HSE

clock

– LSE & LSI clocks are indirectly measured

through MCO by TIM16 timer

(STM32F30/31xx) and TIM14

(STM32F37/38xx) with respect to

HSI/HSE clock

– HSE are indirectly measured through

MCO using TIM16 timer

(STM32F30/31xx) and TIM14

(STM32F37/38xx) channel 1 input capture

with respect to HSI clock.

Table 9. RCC differences between STM32F1 and STM32F3 series (continued)

RCC

STM32F1 series

STM32F3 series

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