RM0312 datasheet(194/275 Pages) STMICROELECTRONICS

194 / 275 page

Inter-integrated circuit (I2C) interface

RM0312

194/275

DocID022352 Rev 3

19.7.10

Status register 3 (I2C_SR3)

Address offset: 0x09

Reset value: 0x00

Note:

Reading I2C_SR3 after reading I2C_SR1 clears the ADDR flag, even if the ADDR flag was

set after reading I2C_SR1. Consequently, I2C_SR3 must be read only when ADDR is found

set in I2C_SR1 or when the STOPF bit is cleared.

654

3210

DUALF

Reserved

GENCALL

Reserved

TRA

BUSY

MSL

Bit 7 DUALF: Dual flag (Slave mode)

0: Received address matched with OAR1

1: Received address matched with OAR2

–

Cleared by hardware after a Stop condition or repeated Start condition, or when PE=0.

Bits 6:5 Reserved

Bit 4 GENCALL: General call header (Slave mode)

0: No general call

1: General call header received when ENGC=1

–

Cleared by hardware after a Stop condition or repeated Start condition, or when PE=0.

Bit 3 Reserved

Bit 2 TRA: Transmitter/Receiver

0: Data bytes received

1: Data bytes transmitted

This bit is set depending on R/W bit of address byte, at the end of total address phase.

It is also cleared by hardware after detection of Stop condition (STOPF=1), repeated Start condition,

loss of bus arbitration (ARLO=1), or when PE=0.

Bit 1 BUSY: Bus busy

0: No communication on the bus

1: Communication ongoing on the bus

–

Set by hardware on detection of SDA or SCL low

–

cleared by hardware on detection of a Stop condition.

It indicates a communication in progress on the bus. This information is still updated when the

interface is disabled (PE=0).

Bit 0 MSL: Master/Slave

0: Slave mode

1: Master mode

–

Set by hardware as soon as the interface is in Master mode (SB=1).

–

Cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration

(ARLO=1), or by hardware when PE=0.

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