RM0312 datasheet(191/275 Pages) STMICROELECTRONICS

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RM0312

Inter-integrated circuit (I2C) interface

200

19.7.8

Status register 1 (I2C_SR1)

Address offset: 0x07

Reset value: 0x00

654

3210

TXE

RXNE

Reserved

STOPF

ADD10

BTF

ADDR

Bit 7 TXE: Data register empty (transmitters) (1)

0: Data register not empty

1: Data register empty

– Set when DR is empty in transmission. TXE is not set during address phase.

– Cleared by software writing to the DR register or by hardware after a start or a stop condition or

when PE=0.

Note: TXE cannot be cleared by writing the first data in transmission or by writing a data when the

BTF bit is set as in both cases, the DR register is still empty.

Bit 6 RXNE: Data register not empty (receivers) (2) (3)

0: Data register empty

1: Data register not empty

– Set when data register is not empty in receiver mode. RXNE is not set during address phase.

– Cleared by software reading or writing the DR register or by hardware when PE=0.

Note: RXE cannot be cleared by reading a data when the BTF bit is set as the DR register is still full

in this case.

Bit 5 Reserved

Bit 4 STOPF: Stop detection (Slave mode) (4)(5)

0: No Stop condition detected

1: Stop condition detected

– Set by hardware when a Stop condition is detected on the bus by the slave after an acknowledge (if

ACK=1).

– Cleared by software reading the SR1 register followed by a write in the CR2 register, or by hardware

when PE=0

Bit 3 ADD10: 10-bit header sent (Master mode) (6)

0: No ADD10 event occurred.

1: Master has sent first address byte (header).

– Set by hardware when the master has sent the first byte in 10-bit address mode.

– Cleared by software reading the SR1 register followed by a write in the DR register of the second

address byte, or by hardware when PE=0.

Bit 2 BTF: Byte transfer finished (7)(8)

0: Data byte transfer not done

1: Data byte transfer succeeded

– Set by hardware when NOSTRETCH=0 and:

–

In reception when a new byte is received (including ACK pulse) and DR has not been read

yet (RXNE=1).

–

In transmission when a new byte should be sent and DR has not been written yet (TXE=1).

– Cleared by software reading SR1 followed by either a read or write in the DR register or by hardware

after a start or a stop condition in transmission or when PE=0.

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