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PM0214 датащи(PDF) 242 Page - STMicroelectronics |
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PM0214 датащи(HTML) 242 Page - STMicroelectronics |
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242 / 245 page ![]() Core peripherals PM0214 242/245 DocID022708 Rev 4 In STM32F4xx devices there is no individual mask and the enable/disable of the FPU interrupt is done at interrupt controller level. In STM32F3xx devices in addition to the FPU interrupt controller interrupt mask bit, there is an individual mask bit for enabling/disabling the FPU interrupt sources (the IXC flag is masked by default in STM32F3xx devices). As it occurs very frequently, the IXC exception flag is not connected to the interrupt controller in STM32F4xx devices, and cannot generate an interrupt. If needed, it must be managed by polling. Clearing the FPU exception flags depends on the FPU context save/restore configuration: • No floating-point register saving: when Floating-point context control register (FPCCR) Bit 30 LSPEN=0 and Bit 31 ASPEN=0. You must clear interrupt source in Floating-point Status and Control Register (FPSCR). Example: register uint32_t fpscr_val = 0; fpscr_val = __get_FPSCR(); { check exception flags } fpscr_val &= (uint32_t)~0x8F; // Clear all exception flags __set_FPSCR(fpscr_val); • Lazy save/restore: when Floating-point context control register (FPCCR) Bit 30 LSPEN=1 and Bit 31 ASPEN=X. In the case of lazy floating-point context save/restore, a dummy read access should be made to Floating-point Status and Control Register (FPSCR) to force state preservation and FPSCR clear. Then handle FPSCR in the stack. Example: register uint32_t fpscr_val = 0; register uint32_t reg_val = 0; reg_val = __get_FPSCR(); //dummy access fpscr_val=*(__IO uint32_t*)(FPU->FPCAR +0x40); { check exception flags } fpscr_val &= (uint32_t)~0x8F ; // Clear all exception flags *(__IO uint32_t*)(FPU->FPCAR +0x40)=fpscr_val; __DMB() ; • Automatic floating-point registers save/restore: when Floating-point context control register (FPCCR) Bit 30 LSPEN=0 and Bit 31 ASPEN=1. In case of automatic floating-point context save/restore, a read access should be made to Floating-point Status and Control Register (FPSCR) to force clear. Then handle FPSCR in the stack. Example: // FPU Exception handler void FPU_ExceptionHandler(uint32_t lr, uint32_t sp) { register uint32_t fpscr_val; if(lr == 0xFFFFFFE9) { sp = sp + 0x60; |
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