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PM0214 датащи(PDF) 173 Page - STMicroelectronics

номер детали PM0214
подробное описание детали  This programming manual provides information
PDF  245 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
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PM0214 датащи(HTML) 173 Page - STMicroelectronics

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PM0214
The STM32 Cortex-M4 instruction set
244
3.11.5
ISB
Instruction synchronization barrier.
Syntax
ISB{cond}
where: ‘cond’ is an optional condition code, see Conditional execution on page 64.
Operation
ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so
that all instructions following the ISB are fetched from cache or memory again, after the ISB
instruction has been completed.
Condition flags
This instruction does not change the flags.
Examples
ISB
; Instruction Synchronisation Barrier
3.11.6
MRS
Move the contents of a special register to a general-purpose register.
Syntax
MRS{cond} Rd, spec_reg
where:
‘cond’ is an optional condition code, see Conditional execution on page 64.
‘Rd’ is the destination register.
‘spec_reg’ can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP,
PSP, PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL.
Operation
Use MRS in combination with MSR as part of a read-modify-write sequence for updating a
PSR, for example to clear the Q flag. See MSR on page 174.
In process swap code, the programmers model state of the process being swapped out
must be saved, including relevant PSR contents. Similarly, the state of the process being
swapped in must also be restored. These operations use MRS in the state-saving
instruction sequence and MSR in the state-restoring instruction sequence.
BASEPRI_MAX is an alias of BASEPRI when used with the MRS instruction.
Restrictions
Rd must not be SP and must not be PC.
Condition flags
This instruction does not change the flags.
Examples



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