PM0214 datasheet(146/245 Pages) STMICROELECTRONICS

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The STM32 Cortex-M4 instruction set

PM0214

146/245

DocID022708 Rev 4

3.9.8

TBB and TBH

Table Branch Byte and Table Branch Halfword.

Syntax

TBB [Rn, Rm]

TBH [Rn, Rm, LSL #1]

where:

•

‘Rn’ is the register containing the address of the table of branch lengths.

If Rn is PC, then the address of the table is the address of the byte immediately

following the TBB or TBH instruction.

•

‘Rm’ is the index register. This contains an index into the table. For halfword tables,

LSL #1 doubles the value in Rm to form the right offset into the table.

Operation

These instructions cause a PC-relative forward branch using a table of single byte offsets for

TBB, or halfword offsets for TBH. Rn provides a pointer to the table, and Rm supplies an

index into the table. For TBB the branch offset is twice the unsigned value of the byte

returned from the table. and for TBH the branch offset is twice the unsigned value of the

halfword returned from the table. The branch occurs to the address at that offset from the

address of the byte immediately after the TBB or TBH instruction.

Restrictions

The restrictions are:

•

Rn must not be SP

•

Rm must not be SP and must not be PC

•

When any of these instructions is used inside an IT block, it must be the last instruction

of the IT block.

Condition flags

These instructions do not change the flags.

Examples

ADR.W

R0, BranchTable_Byte

TBB [R0, R1] ; R1 is the index, R0 is the base address of the branch table

Case1

; an instruction sequence follows

Case2

; an instruction sequence follows

Case3

; an instruction sequence follows

BranchTable_Byte

DCB

; Case1 offset calculation

DCB

((Case2-Case1)/2)

; Case2 offset calculation

DCB

((Case3-Case1)/2)

; Case3 offset calculation

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