PM0214 datasheet(129/245 Pages) STMICROELECTRONICS

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PM0214

The STM32 Cortex-M4 instruction set

244

QSAX R0, R3, R5

; Subtracts bottom halfword of R5 from top halfword of

; R3, saturates to 16 bits, writes to top halfword of R0

; Adds bottom halfword of R3 to top halfword of R5,

; saturates to 16 bits, writes to bottom halfword of R0.

3.7.5

QDADD and QDSUB

Saturating Double and Add and Saturating Double and Subtract, signed.

Syntax

op{cond} {Rd}, Rm, Rn

where:

•

op’ is one of:

QDADD Saturating Double and Add.

QDSUB Saturating Double and Subtract.

•

‘cond’ is an optional condition code (see Conditional execution on page 64)

•

‘Rd’ is the destination register.

•

‘Rn, Rm’ are registers holding the first and second operands.

Operation

The QDADD instruction:

Doubles the second operand value.

Adds the result of the doubling to the signed saturated value in the first operand.

Writes the result to the destination register.

The QDSUB instruction:

Doubles the second operand value.

Subtracts the doubled value from the signed saturated value in the first operand.

Writes the result to the destination register.

Both the doubling and the addition or subtraction have their results saturated to the 32-bit

signed integer range –231

≤x ≤231– 1. If saturation occurs in either operation, it sets the Q

flag in the APSR.

Restrictions

Do not use SP and do not use PC.

Condition flags

If saturation occurs, these instructions set the Q flag to 1.

Examples

QDADD

R7, R4, R2

; Doubles and saturates R4 to 32 bits, adds R2,

; saturates to 32 bits, writes to R7

QDSUB

R0, R3, R5

; Subtracts R3 doubled and saturated to 32 bits

; from R5, saturates to 32 bits, writes to R0.

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