AN4031 datasheet(33/36 Pages) STMICROELECTRONICS

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AN4031

Tips and warnings while programming the DMA controller

Twice-mapped DMA requests

When the user configures two (or more) DMA streams to serve the same peripheral request,

software should ensure that the current DMA stream is completely disabled (by polling the

EN bit in the DMA_SxCR register) before enabling a new DMA stream.

Best DMA throughput configuration

When using STM32F4xx with reduced AHB frequency while DMA is servicing a high-speed

peripheral, it is recommended to put the stack and heap in the CCM (which can be

addressed directly by the CPU through D-bus) instead of putting them on the SRAM, which

would create an additional concurrency between CPU and DMA accessing the SRAM

memory.

DMA transfer suspension

At any time, a DMA transfer can be suspended to be restarted later on or to be definitively

disabled before the end of the DMA transfer.

There are two cases:

•

The stream disables the transfer with no later-on restart from the point where it was

stopped: there is no particular action to do, except to clear the EN bit in the DMA_SxCR

–

The DMA_SxNDTR register contains the number of remaining data items at the

moment when the stream was stopped so that the software can determine how

many data items have been transferred before the stream was interrupted.

•

The stream suspends the transfer in order to resume it later by re-enabling the stream:

to restart from the point where the transfer was stopped, the software has to read the

DMA_SxNDTR register after disabling the stream (EN bit at “0”) to know the number of

data items already collected. Then:

–

The peripheral and/or memory addresses have to be updated in order to adjust

the address pointers.

–

The SxNDTR register has to be updated with the remaining number of data items

to be transferred (the value read when the stream was disabled).

–

The stream may then be re-enabled to restart the transfer from the point where it

was stopped.

Note:

In both cases, a Transfer Complete Interrupt Flag (TCIF in DMA_LISR or DMA_HISR) is set

to indicate the end of transfer due to the stream interruption.

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