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AN4031

How to predict DMA latencies

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3.2

Examples

3.2.1

ADC-to-SRAM DMA transfer

This example is applicable to products STM32F2xx, STM32F405, STM32F407,

STM32F415, STM32F417, STM32F42x and STM32F43x.

The ADC is configured in continuous triple Interleaved mode. In this mode, it converts

continuously one analog input channel at the maximum ADC speed (36 MHz). The ADC

prescaler is set to 2, the sampling time is set to 1.5 cycles, and the delay between two

consecutive ADC samples of the Interleaved mode is set to 5 cycles.

The DMA2 stream0 transfers the ADC converted value to an SRAM buffer. DMA2 access to

ADC is done through direct path; however, DMA access to SRAM is done through the bus

matrix.

In this example, the total DMA latency from the ADC DMA trigger (ADC EOC) to write the ADC value

on SRAM is equal to 9 AHB cycles for AHB/APB prescaler equals 1 and 11 AHB cycles for AHB/APB

prescaler equals 2.

Note:

When using FIFO, the DMA memory port access is launched when reaching the FIFO level

configured by the user.

Table 9. DMA peripheral (ADC) port transfer latency

AHB/APB2 frequency

AHB/APB ratio = 1

FAHB = 144 MHz/

FAPB2 = 72 MHz

AHB/APB ratio = 2

Transfer time

1 AHB cycle

1 AHB cycle

1 AHB cycle

1 AHB cycle

1. DMA2 accesses ADC through direct path: no bus matrix arbitration.

N/A(1)

2 AHB cycles

4 AHB cycles

1 AHB cycle

1 AHB cycle

5 AHB cycles

7 AHB cycles

Table 10. DMA memory (SRAM) port transfer latency

CPU/APB2 frequency

FAHB = 72MHz/

FAPB2=72MHz

AHB/APB ratio = 1

FAHB = 144MHz/

FAPB2=72MHz

AHB/APB ratio = 2

Transfer time

1 AHB cycle

1 AHB cycle

1 AHB cycle

1 AHB cycle

1. In case of DMA multiple access to SRAM, the bus matrix arbitration is equal to 0 cycle if no other master

accessed to the SRAM in-between.

1 AHB cycle(1)

1 AHB cycle

1 AHB cycle

4 AHB cycles

4 AHB cycles