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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AN4031 датащи(PDF) 23 Page - STMicroelectronics |
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AN4031 датащи(HTML) 23 Page - STMicroelectronics |
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23 / 36 page  DocID022648 Rev 1 23/36 AN4031 System performance considerations 35 2.2.2 DMA transfer states This section explains the DMA transfer steps at the peripheral port level and also at the memory port level: • For a peripheral-to-memory transfer: In this transfer mode, DMA requires two bus accesses to perform the transfer: – One access over the peripheral port triggered by the peripheral’s request, – One access over the memory port which can be triggered either by the FIFO threshold (when FIFO mode is used) or immediately after peripheral read (when Direct mode is used). Figure 12. Peripheral-to-memory transfer states • For a memory-to-peripheral transfer: In this transfer mode, DMA requires two bus accesses to perform the transfer: – DMA anticipates the peripheral’s access and reads data from the memory and stores it in FIFO to ensure an immediate data transfer as soon as a DMA peripheral request is triggered. – When a peripheral request is triggered, a transfer is generated on the DMA peripheral port. |
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