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PM0044 датащи(PDF) 26 Page - STMicroelectronics

номер детали PM0044
подробное описание детали  STM8 CPU programming manual
PDF  162 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PM0044 датащи(HTML) 26 Page - STMicroelectronics

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Pipelined execution
PM0044
26/162
Doc ID 13590 Rev 3
5.4.2
Optimize pipeline example – execution from RAM
In the example shown in Table 8, the RAM is accessed through an 8-bit bus. As a result, 12
cycles are required to fill the 96-bit pre-fetch buffer. Every 4 cycles, one word is loaded and
stored in Fx. The decoding of the first word instruction can start only when the Fx word is
filled. This occurs for example till the 4th cycle, and the first instruction (NEG A) can be
decoded only at the 5th cycle.
In case of read/write access to the RAM, the fetch is stalled. This occurs during the 6th cycle
since RAM address 10 is read during the decode stage of XOR A, $10.
Table 8.
Optimize pipeline example – execution from RAM
Add.
Cycle
1
2
3
4
5
6
7
8
9
10 11
12
13
14 15 16 17 18
19 20 21
0xC000
NEG A
1
1
1
D
D
D
D
E
0xC001
XOR A,
$10
11
2
D
E
0xC003
LD A, #20
1
1
2
D
D
D
D
E
0xC005
SUB
A,$1000
11
3
FS
D
E
0xC008
INC A
1
1
1
D
D
D
D
E
0xC009
LD XL, A
1
1
1
FS
D
E
0xC00A
SRL A
1
1
1
D
E
0xC00B
SWAP A
1
1
1
D
E
0xC00C
SLA $15
1
1
2
D
E
0xC00E
CP
A,#$FE
11
2
D
E
Table 9.
Legend
Symbol/Color
Definition
FFetch
FS
Fetch stalled
DDecode
D
Decode stalled
EExecute



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