PM0044 datasheet(21/162 Pages) STMICROELECTRONICS

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PM0044

Pipelined execution

Doc ID 13590 Rev 3

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Figure 6.

Pipelined execution stages

5.1.1

Fetch stage

The first pipeline stage includes a 64-bit fetch buffer and a 32-bit prefetch buffer, totalling 3

words named F1, F2 and F3. This buffer structure allows any instruction code (up to 5 bytes)

to be available for decoding immediately after F1 (and F2 when needed) is/are loaded.

The instruction access from Flash Program memory is 32-bit wide and it is performed from

an aligned address i.e. 0xXXX0, 0xXXX4, 0xXXX8, or 0xXXXC.

Unlike the decode and execute stages that are performed at every cycle, the fetch stage

accesses the program memory only when needed, and stops memory access when the

buffer is full. This allows reducing the core power consumption,

Reading program from RAM is similar to reading program from ROM. However, since the

RAM data bus is 8-bit wide, 4 consecutive read operations have to be performed to load one

FX word, thus resulting in RAM execution being slower than Flash execution.

5.1.2

Decoding and addressing stage

The decoding stage includes an instruction alignment unit. The alignment unit uses the 64-

bit input from the fetch unit and feeds an instruction (from 1 to 5 bytes depending on the

instruction) to the decoding unit.

The instruction code consists of 2 parts (see examples in Table 2):

●

The op-code itself (1 or 2 bytes)

●

and a data/address part (0 to 3 bytes).

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