PM0044 datasheet(15/162 Pages) STMICROELECTRONICS

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PM0044

STM8 core description

Doc ID 13590 Rev 3

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Global configuration register (CFG_GCR)

The global configuration register is a memory mapped register. It controls the configuration

of the processor. It contains the AL control bit:

AL: Activation level

If the AL bit is 0 (main), the IRET will cause the context to be retrieved from stack and the

main program will continue after the WFI instruction.

If the AL bit is 1 (interrupt only active), the IRET will cause the CPU to go back to WFI/HALT

mode without restoring the context.

This bit is used to control the low power modes of the MCU. In a very low power application,

the MCU spends most of the time in WFI/HALT mode and is woken up (through interrupts)

at specific moments in order to execute a specific task. Some of these recurring tasks are

short enough to be treated directly in an ISR, rather than going back to the main program. In

this case, by programming the AL bit to 1 before going to low power (by executing WFI/HALT

instruction), the run time/ISR execution is reduced due to the fact that the register context is

not saved/restored each time.

Condition Code register (CC)

The Condition Code register is a 8-bit register which indicates the result of the instruction

just executed as well as the state of the processor. These bits can be individually tested by a

program and specified action taken as a result of their state. The following paragraphs

describe each bit.

●

V: Overflow

When set, V indicates that an overflow occurred during the last signed arithmetic

operation, on the MSB operation result bit. See INC, INCW, DEC, DECW, NEG, NEGW,

ADD, ADC, SUB, SUBW, SBC, CP, CPW instructions.

●

I1: Interrupt mask level 1

The I1 flag works in conjunction with the I0 flag to define the current interruptability level

as shown in the following table. These flags can be set and cleared by software through

the RIM, SIM, HALT, WFI, IRET, TRAP and POP instructions and are automatically set

by hardware when entering an interrupt service routine.

●

H: Half carry bit

The H bit is set to 1 when a carry occurs between the bits 3 and 4 of the ALU during an

ADD or ADC instruction. The H bit is useful in BCD arithmetic subroutines.

For ADDW, SUBW it is set when a carry occurs from bit 7 to 8, allowing to implement

byte arithmetic on 16-bit index registers.

Table 1.

Interruptability levels

Interruptability

Priority

Interruptable Main

Lowest

↕

Highest

Interruptable Level 1

Interruptable Level 2

Non Interruptable

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