Pad descriptions and configurations

AN3100

20/24

Doc ID 16606 Rev 2

7.1

DDR_PAD register configuration

The pads should be configured according to the type of memory in use (DDR MOBILE or

DDR2)

In the DDR_PAD register, Bits [18:15] and bit [0] are used in conjunction with pin

DDR2_EN to configure the pads in hardware or software mode.

●

Bits [18:15] = 0000: hardware configuration mode.

In this mode, the input level of the DDR2_EN pin selects the configuration

(DDR2_EN =1 = configuration for DDR2) and DDR_PAD register [0] is don’t care.

●

Bits [18:15] = 0110: software configuration mode.

In this mode, the value of DDR_PAD register [0] selects the configuration]

(1 = configuration for DDR2) and pin DDR2_EN is don’t care.

All other combinations are not allowed.

Bit [14] is a status bit and reflects the status of the pin DDR2_EN.

All these settings establish the value for the pin DDR2V5 of pad data and clock cells and

configure them to operate properly on the basis of the memory type attached.

Bit [13] establishes the nature of the common reference for all SSTL pads.

0 = internal reference and

1 = external reference.

It is recommended to use an external reference to improve the stability.

Bit [12] Controls GATE_OPEN_MODE. It should be set to 1 in normal operating conditions.

Bit [11] is reserved.

Bit [10] Controls the pad ENZI signal (input buffer enable). It should be 0 in normal

operating conditions.

Bits [9: 8] respectively control the pull-up and the pull-down of pins PDNCLK2V5 and

PUPCLK2V5 of the pad clock cells for the DDR_MEM_DQS[1:0] pads.See Table 5 for the

settings.

Bits [7: 6] respectively control the pull-up and the pull-down of pins PDNCLK2V5 and

PDNCLKB2V5 of the pad clock cell for the DDR_MEM_CLKP/N pads.See Table 5 for the

settings.

Bits [5: 4] control the pull-up and the pull-down of the pins PU2V5 and PDN2V5 of all pad

data cells.See Table 5 for the settings.

Bits [3: 1] respectively control the pins ZPROGOUTA2V5, PROGA2V5, PROGB2V5 for all

pad data and clock cells.

Table 5.

Pull-up and pull down settings

Bit pair value

Meaning

00

pull-down active and pull-up not active

01

forbidden

10

pull-down not active and pull-up not active (default)

11

pull-down not active and pull-up active